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RTR532
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01e4a4b6d37e916795e2526c3d43838a8ede2746
RTR532
/
ld3
/
dds_vhdl
T
History
imants
01e4a4b6d3
Signal sum and signal sum test bench now working.
...
Added overflow check logic
2020-06-09 14:40:44 +03:00
..
sin_gen_sum_tb.vhd
Signal sum and signal sum test bench now working.
2020-06-09 14:40:44 +03:00
sin_gen_sum.vhd
Signal sum and signal sum test bench now working.
2020-06-09 14:40:44 +03:00
sin_gen_tb.vhd
Added clock divider 22050Hz. Tested!
2020-06-09 00:04:30 +03:00
sin_gen.qpf
Added clock divider 22050Hz. Tested!
2020-06-09 00:04:30 +03:00
sin_gen.qsf
Signal sum and signal sum test bench now working.
2020-06-09 14:40:44 +03:00
sin_gen.vhd
Added clock divider 22050Hz. Tested!
2020-06-09 00:04:30 +03:00
