104 lines
2.4 KiB
Verilog
104 lines
2.4 KiB
Verilog
/////////////////////////////////////////////////////////////////
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// Author - Imants Pulkstenis
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// Date - 23.02.2020
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// Project name - PS03
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// Module name - Testbench for Smart traffic light controler
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//
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// Detailed module description:
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//
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// Generating the stimulation
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// Clk - Generate the 1GHz clock input
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// Rst - generate both high and low reset to ensure correct start up, per Required functionality
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// MR_cars - generate multiple values to simulate real world traffic situation (e.g. at night some
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// cars arrive once per 60nanoseconds, in day – more cars) and verify that smart traffic light controller is working correctly.
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//
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// The test can be executed using Icarus Verilog!
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// The result can be evaluated in GTKwave application.
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// Code:
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// iverilog -o output.vvp tlc_tb.v && vvp output.vvp
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// gtkwave -f wave.vcd
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//
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// Revision:
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// A - initial design
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// B -
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// C -
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//
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///////////////////////////////////////////////////////////////////
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//UUT module
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`include "traffic_light_controller.v"
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// 1GHz clock -> 1ns period
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// 50% duty cycle 0.5ns HIGH and 0.5ns LOW
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// `timescale [time unit] / [time precision]
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`timescale 1ns / 100ps
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//define module
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module tlc_tb ();
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//define inside use signals
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reg clk = 1'b0;
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reg rst = 1'b1;
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reg [7:0] MR_cars = 'b0;
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integer ii=0;
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//---------Test script----------------
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// 50% duty cycle clock
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always #0.5 clk <= ~clk;
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//-----Unit Under test---------------
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traffic_light_controller #(
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.PARAMETER(45)
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) unit_under_test (
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.clk(clk),
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.rst(rst),
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.MR_cars(MR_cars),
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.MR_ctl(),
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.SR_ctl());
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//---------Reset Test--------------------
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initial begin
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rst = 0;
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#10;
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rst = 1;
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#200
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rst = 0;
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#100;
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rst = 1;
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end
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initial
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begin
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//---------Daytime traffic Test--------------------
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for (ii=0; ii<50; ii=ii+1)
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begin
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MR_cars = ii;
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#10;
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end
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MR_cars = 0;
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#100;
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//---------Nighttime traffic Test--------------------
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for (ii=0; ii<50; ii=ii+1)
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begin
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MR_cars = ii;
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#60;
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end
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#100;
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$finish();
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end
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// just print text
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initial begin
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$display(" ");
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$display("----------------------------------------------");
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$display(" Starting Testbench...");
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$dumpfile("wave.vcd");
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$dumpvars(0);
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$display("----------------------------------------------");
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$display(" ");
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end
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endmodule |