65 lines
1.1 KiB
VHDL
65 lines
1.1 KiB
VHDL
----------------------------- info header [part 1 of the VHDL file]
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-- Author
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-- Date
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-- Project name
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-- Module name
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--
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-- Detailed module description
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--
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--
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--
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--
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--
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--
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--
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-- Revision:
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-- A - initial design
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-- B -
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--
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-----------------------------
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-- define libraries to be used [part 2 of the VHDL file]
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library ieee; --always use this library
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use ieee.std_logic_1164.all; --always use this library
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use ieee.numeric_std.all; --use this library if arithmetic required
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--Entity declaration [part 3 of the VHDL file].
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entity alu is
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generic
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(
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data_width : integer := 32
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);
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port
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(
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clk : in std_logic;
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A : in std_Logic_vector(data_width - 1 downto 0);
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B : in std_logic_vector(data_width - 1 downto 0);
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op : in std_logic_vector(3 downto 0);
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R : out std_logic_vector(data_width - 1 downto 0);
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flag : out std_logic
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);
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end alu;
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--define inside of the module
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architecture behavioral of alu is
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--define inside use signals and components [part 4 of the VHDL file]
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begin
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--define the operation of the module! [part 5 of the VHDL file]
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flag <= '0'; --optional
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end behavioral;
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