73 lines
2.3 KiB
Verilog
73 lines
2.3 KiB
Verilog
///////////////////////////// info header [part 1 of the Verliog file]
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// Author - Imants Pulkstenis
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// Date - 16.02.2020
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// Project name - PS02
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// Module name - alu
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//
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// Detailed module description:
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//
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// Arithmetic Logic Unit for PS02 project
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//
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//
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//
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//
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// Revision:
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// A - initial design
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// B - VHDL code are replaced with Verilog
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// C - ALU logic defined in module
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//
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/////////////////////////////
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//no need for libraries [part 2 of the Verilog file]
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//Entity declaration [part 3 of the Verilog file].
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module alu #( parameter
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data_width = 32
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)(
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input clk,
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input [data_width - 1:0] A,
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input [data_width - 1:0] B,
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input [3:0] op,
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output [data_width - 1:0] R,
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output flag);
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//define inside of the module
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//define inside use signals and components [part 4 of the VHDL file]
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reg [data_width -1 :0] reg_R = 'h0;
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//define the operation of the module! [part 5 of the VHDL file]
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always@(posedge clk) begin
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case (op)
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4'h0: reg_R <= (A - B);
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4'h1: reg_R <= (A + B);
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4'h2: reg_R[data_width - 1:0] <= ~(A & B);
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4'h3: reg_R[data_width - 1:0] <= (A & B);
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4'h4: reg_R[data_width - 1:0] <= (A | B);
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4'h5: reg_R[data_width - 1:0] <= ~(A | B);
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4'h6: reg_R[data_width - 1:0] <= (A ^ B);
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4'h7: reg_R[data_width - 1:0] <= ~A;
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4'h8: reg_R[data_width - 1:0] <= ~B;
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4'h9: reg_R <= B + 1;
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4'ha: reg_R <= A + 1;
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4'hb: reg_R <= A - 1;
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4'hc: reg_R <= B - 1;
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4'hd: reg_R[data_width - 1:0] <= A << 1; // << Shift Left, Logical (fill with zero)
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// <<< Shift Left, Arithmetic (keep sign)
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4'he: reg_R[data_width - 1:0] <= A >> 1; // >> Shift Right, Logical (fill with zero)
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// >>> Shift Right, Arithmetic (keep sign)
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4'hf: reg_R[data_width - 1:0] <= 'b0;
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default: reg_R[data_width - 1:0] <= 'b0;
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endcase
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end
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assign R = reg_R;
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assign flag = 1'b0; //optional
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endmodule
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