3 Commits

Include renames

Author	SHA1	Message	Date
Imants Pulkstenis	fcc5a0b050	Compleated Verilog file and started working un VHDL	2020-02-23 22:40:30 +02:00
Imants Pulkstenis	c42e0654da	add aditional else if for MR_GREEN_1 state	2020-02-23 19:18:36 +02:00
Imants Pulkstenis	e6cbc865aa	Add Problem set 3	2020-02-23 19:12:32 +02:00