FIR and IIR filter and test benches are now working

ld3/dds_vhdl/fir.qip

@@ -26,9 +26,9 @@ set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAM
 set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "c3ltbWV0cnlNb2Rl::bnN5bQ==::U3ltbWV0cnk="
 set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "TF9iYW5kc0ZpbHRlcg==::MQ==::TC10aCBCYW5kIEZpbHRlcg=="
 set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "aW5wdXRDaGFubmVsTnVt::MQ==::TWF4IE51bWJlciBvZiBDaGFubmVscw=="
-set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y2xvY2tSYXRl::MTAw::Q2xvY2sgUmF0ZQ=="
+set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y2xvY2tSYXRl::MC4wMjIwNQ==::Q2xvY2sgUmF0ZQ=="
 set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y2xvY2tTbGFjaw==::MA==::Q2xvY2sgU2xhY2s="
-set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "aW5wdXRSYXRl::MTAw::SW5wdXQgU2FtcGxlIFJhdGUgKE1TUFMp"
+set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "aW5wdXRSYXRl::MC4wMjIwNQ==::SW5wdXQgU2FtcGxlIFJhdGUgKE1TUFMp"
 set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y29lZmZSZWxvYWQ=::ZmFsc2U=::Q29lZmZpY2llbnRzIFJlbG9hZA=="
 set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y29lZmZpY2llbnRSZWFkYmFjaw==::ZmFsc2U=::Y29lZmZpY2llbnRSZWFkYmFjaw=="
 set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y29lZmZpY2llbnRXcml0ZWFibGU=::ZmFsc2U=::Y29lZmZpY2llbnRXcml0ZWFibGU="

ld3/dds_vhdl/fir.vhd

@@ -83,9 +83,9 @@ end architecture rtl; -- of fir
 -- Retrieval info: 	<generic name="symmetryMode" value="nsym" />
 -- Retrieval info: 	<generic name="L_bandsFilter" value="1" />
 -- Retrieval info: 	<generic name="inputChannelNum" value="1" />
--- Retrieval info: 	<generic name="clockRate" value="100" />
+-- Retrieval info: 	<generic name="clockRate" value="0.02205" />
 -- Retrieval info: 	<generic name="clockSlack" value="0" />
--- Retrieval info: 	<generic name="inputRate" value="100" />
+-- Retrieval info: 	<generic name="inputRate" value="0.02205" />
 -- Retrieval info: 	<generic name="coeffReload" value="false" />
 -- Retrieval info: 	<generic name="baseAddress" value="0" />
 -- Retrieval info: 	<generic name="readWriteMode" value="read_write" />

ld3/dds_vhdl/fir/fir_0002_rtl_core.vhd

@@ -16,7 +16,7 @@
 -- ---------------------------------------------------------------------------
 
 -- VHDL created from fir_0002_rtl_core
--- VHDL created on Tue Jun 09 18:16:08 2020
+-- VHDL created on Wed Jun 10 17:16:42 2020
 
 
 library IEEE;

ld3/dds_vhdl/fir_sim/aldec/rivierapro_setup.tcl

@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 19.1 670 win32 2020.06.09.18:16:15
+# ACDS 19.1 670 win32 2020.06.10.17:16:48
 # ----------------------------------------
 # Auto-generated simulation script rivierapro_setup.tcl
 # ----------------------------------------

ld3/dds_vhdl/fir_sim/cadence/ncsim_setup.sh

@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 19.1 670 win32 2020.06.09.18:16:15
+# ACDS 19.1 670 win32 2020.06.10.17:16:48
 
 # ----------------------------------------
 # ncsim - auto-generated simulation script
@@ -106,7 +106,7 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 19.1 670 win32 2020.06.09.18:16:15
+# ACDS 19.1 670 win32 2020.06.10.17:16:48
 # ----------------------------------------
 # initialize variables
 TOP_LEVEL_NAME="fir"

ld3/dds_vhdl/fir_sim/fir_input.txt

@@ -81,47 +81,47 @@
 0 
 0 
 0 
--6804 
+10987 
--7424 
+-13679 
--9673 
+-16074 
-11030 
+-30691 
--17117 
+3112 
-13591 
+16798 
--31248 
+-1713 
-14940 
+-25728 
--21868 
+-8040 
--17002 
+-9094 
--15878 
+-24258 
--7873 
+-5223 
--18900 
+20803 
--9386 
+16580 
--14628 
+8315 
-32567 
+32333 
-4720 
+-1475 
--19739 
+31169 
--13837 
+31412 
-12911 
+81 
-16220 
+-4422 
--18003 
+-16781 
--2374 
+12806 
-3596 
+21929 
-24737 
+-3569 
--4863 
+-19942 
--24276 
+-21913 
-20032 
+15493 
-31499 
+22121 
-14450 
+15586 
-98 
+21871 
-9422 
+2677 
-25309 
+-24068 
--10432 
+-30569 
--29523 
+13816 
--30326 
+18877 
--28282 
+13314 
--18678 
+-21445 
--10718 
+11509 
-14639 
+-22882 
-26177 
+-24684 
 0 
 0 
 0 

ld3/dds_vhdl/fir_sim/fir_model.m

@@ -19,7 +19,7 @@
 % their respective licensors.  No other licenses, including any licenses
 % needed under any third party's intellectual property, are provided herein.
 % ================================================================================
-% Generated on: 06/09/2020 18:16:10
+% Generated on: 06/10/2020 17:16:45
 % Generated by: FIR Compiler II 19.1
 %---------------------------------------------------------------------------------------------------------
 %

ld3/dds_vhdl/fir_sim/fir_param.txt

@@ -10,8 +10,8 @@ OutFracWidth : 28
 OutFullFracWidth : 28 
 nChans : 41 
 nTaps : 41 
-clockRate : 100 
+clockRate : 0.02205 
-inRate : 100 
+inRate : 0.02205 
 interpN : 1 
 decimN : 1 
 busDataWidth : 16 

ld3/dds_vhdl/fir_sim/fir_rtl_core.vhd

@@ -16,7 +16,7 @@
 -- ---------------------------------------------------------------------------
 
 -- VHDL created from fir_rtl_core
--- VHDL created on Tue Jun 09 18:16:09 2020
+-- VHDL created on Wed Jun 10 17:16:42 2020
 
 
 library IEEE;

ld3/dds_vhdl/fir_sim/mentor/msim_setup.tcl

@@ -94,7 +94,7 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 19.1 670 win32 2020.06.09.18:16:15
+# ACDS 19.1 670 win32 2020.06.10.17:16:48
 
 # ----------------------------------------
 # Initialize variables

ld3/dds_vhdl/fir_sim/synopsys/vcsmx/vcsmx_setup.sh

@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 19.1 670 win32 2020.06.09.18:16:15
+# ACDS 19.1 670 win32 2020.06.10.17:16:48
 
 # ----------------------------------------
 # vcsmx - auto-generated simulation script
@@ -107,7 +107,7 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 19.1 670 win32 2020.06.09.18:16:15
+# ACDS 19.1 670 win32 2020.06.10.17:16:48
 # ----------------------------------------
 # initialize variables
 TOP_LEVEL_NAME="fir"

ld3/dds_vhdl/lab3.vhd

@@ -28,8 +28,8 @@ entity lab3 is
     (
         phase_width                     : integer := 9;
         data_width                      : integer := 16;
-        phase_incr_one                  : integer := 37;    -- 22050/1664
+        phase_incr_one                  : integer := 37;    -- Ph_inc = (f_out * 2^(B_n))/f_clk
-        phase_incr_two                  : integer := 57;
+        phase_incr_two                  : integer := 57;    -- 2496 * 2^9 / 22050
         sampling_f						: integer := 4535;	-- 100MHz/22050
 	    clock_cnt_width					: integer := 13
     );
@@ -45,8 +45,9 @@ architecture behavioral of lab3 is
     --define inside use signals
     signal signal_f_one                   : std_Logic_vector(data_width - 1 downto 0) := (others => '0');
     signal signal_f_two                   : std_Logic_vector(data_width - 1 downto 0) := (others => '0');
-	 signal signal_sum                     : std_Logic_vector(data_width - 1 downto 0) := (others => '0');
+	signal signal_sum                     : std_Logic_vector(data_width - 1 downto 0) := (others => '0');
-	 signal clk_22050                      : std_Logic := '0';    
+	signal clk_22050                      : std_Logic := '0'; 
+	signal not_rst                        : std_Logic := '1';  
 
     --define components to use
 	component sin_gen is
@@ -111,6 +112,9 @@ architecture behavioral of lab3 is
 
 begin	--define the operation of the module!
 
+not_rst <= std_logic(not rst);
+
+
 sin_gen_one : sin_gen   -- first signal generator
 generic map
 (
@@ -176,14 +180,14 @@ port map
 fir_one : fir    -- FIR filter from Altera Megawizard plugin IP Core
 port map
 ( 
-				clk                               =>  clk,           --  clk.clk
+				clk                               =>  clk_22050,			 	--  clk.clk
-            reset_n                                =>  rst,          --  rst.reset_n
+            reset_n                           =>  not_rst,   				--  rst.reset_n
-            ast_sink_data                               => signal_sum,--   avalon_streaming_sink.data
+            ast_sink_data                     =>  signal_sum,				--   avalon_streaming_sink.data
-            ast_sink_valid                               =>   '1',         --  .valid
+            ast_sink_valid                    =>  '1',         			--  .valid
-            ast_sink_error                                  => "00"  -- .error
+            ast_sink_error                    =>  "00"  						-- .error (00: No error)
-         --   ast_source_data                                 =>                    -- avalon_streaming_source.data
+         --   ast_source_data                                 =>           -- avalon_streaming_source.data
-         --   ast_source_valid                                =>                                    --    .valid
+         --   ast_source_valid                                =>           --    .valid
-         --   ast_source_error                                =>                     --   .error
+         --   ast_source_error                                =>           --   .error
 );
 
 

ld3/dds_vhdl/sin_gen.qsf

@@ -39,7 +39,7 @@
 
 set_global_assignment -name FAMILY "Cyclone V"
 set_global_assignment -name DEVICE 5CGXFC7C7F23C8
-set_global_assignment -name TOP_LEVEL_ENTITY lab3
+set_global_assignment -name TOP_LEVEL_ENTITY sin_gen_sum
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:16:23  MARCH 21, 2018"
 set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
@@ -54,12 +54,10 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name VHDL_FILE lab3_tb.vhd
-set_global_assignment -name VHDL_FILE lab3.vhd
 set_global_assignment -name VHDL_FILE sin_gen_sum_tb.vhd
 set_global_assignment -name VHDL_FILE sin_gen_sum.vhd
 set_global_assignment -name VHDL_FILE sin_gen_tb.vhd
 set_global_assignment -name VHDL_FILE sin_gen.vhd
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 set_global_assignment -name QIP_FILE fir.qip
 set_global_assignment -name SIP_FILE fir.sip
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

ld3/dds_vhdl/sin_gen.vhd

@@ -22,7 +22,7 @@ use ieee.numeric_std.all;		--use this library if arithmetic required
 entity sin_gen is
 generic
 (
-	phase_width							: integer := 9;
+	phase_width 						: integer := 9;
 	data_width							: integer := 16;
 	sampling_f							: integer := 4535;	-- 100MHz/22050
 	clock_cnt_width						: integer := 13
@@ -585,9 +585,9 @@ begin	--define the operation of the module!
 			else
 				if  clock_cnt <= sampling_f then
 					clock_cnt <= unsigned(clock_cnt) + 1;
-					if clock_cnt = (sampling_f-1)/2 then
+					--if clock_cnt = (sampling_f-1)/2 then
-						clock_out <= not clock_out;
+					--	clock_out <= not clock_out;
-					end if;
+					--end if;
 				else
 					phase_cnt <= unsigned(phase_cnt) + unsigned(phase_incr);
 					clock_cnt <= (others => '0');

ld3/dds_vhdl/sin_gen_sum.vhd

@@ -26,9 +26,7 @@ entity sin_gen_sum is
     generic
     (
         phase_width                     : integer := 9;
-        data_width                      : integer := 16--;
+        data_width                      : integer := 16
-        --phase_incr_one                  : integer := 37;
-        --phase_incr_two                  : integer := 57
     );
     port
     (
@@ -42,66 +40,15 @@ entity sin_gen_sum is
 
 --define inside of the module
 architecture behavioral of sin_gen_sum is
-    --define inside use signals
-    --signal signal_out_one                   : std_Logic_vector(data_width - 1 downto 0) := (others => '0');
-    --signal signal_out_two                   : std_Logic_vector(data_width - 1 downto 0) := (others => '0');
-	signal signal_summ                      : signed(data_width - 1 downto 0) := (others => '0'); --  16bit word
 
-    --define components to use
+    signal signal_summ                      : signed(data_width - 1 downto 0) := (others => '0'); --  16bit word
-	-- component sin_gen is
+     
-    --     generic
-    --     (
-    --         phase_width 						: integer := 9;
-    --         data_width							: integer := 16
-    --     );
-    --     port
-    --     (
-    --         clk 								: in std_logic;	--100mhz clock
-    --         rst									: in std_logic;	--rst
-    --         --phase_incr							: in std_Logic_vector(phase_width - 1 downto 0); --"frequency"
-    --         signal_f_one                        : out std_Logic_vector(data_width - 1 downto 0); --
-    --         signal_f_two                        : out std_Logic_vector(data_width - 1 downto 0);
-    --         --phase_out							: out std_Logic_vector(phase_width - 1 downto 0);
-    --         signal_out							: out std_Logic_vector(data_width - 1 downto 0)
-    --     );
-    --     end component;
 
 begin	--define the operation of the module!
     --signal output 
     
 	signal_out <= std_logic_Vector(signal_summ);
 
-
--- sin_gen_one : sin_gen 
--- generic map
--- (
---     phase_width 						=> phase_width,
---     data_width							=> data_width
--- )
--- port map
--- (
---     clk 							    	=> clk,
---     rst									=> rst,
---     phase_incr							=> std_logic_Vector(To_unsigned(phase_incr_one,phase_width)),
---     --phase_out						=> phase_out,
---     signal_out							=> signal_out_one
--- );
-
--- sin_gen_two : sin_gen 
--- generic map
--- (
---     phase_width 						=> phase_width,
---     data_width							=> data_width
--- )
--- port map
--- (
---     clk 							    	=> clk,
---     rst									=> rst,
---     phase_incr							=> std_logic_Vector(To_unsigned(phase_incr_two,phase_width)),
---     --phase_out						=> phase_out,
---     signal_out							=> signal_out_two
--- );
-
 	--adder
 	process(clk)
 	begin

ld3/dds_vhdl/sin_gen_sum_tb.vhd

@@ -10,7 +10,7 @@
 --
 -- Revision:
 -- A - initial design
--- B - 
+-- B - Remove sin_gen module out of this module
 --
 -----------------------------
 library ieee;					--always use this library
@@ -24,58 +24,122 @@ entity sin_gen_sum_tb is
     (
         phase_width 						: integer := 9;
         data_width							: integer := 16;
-		  phase_incr_one                      : integer := 37;
+	    phase_incr_one                      : integer := 37;
-        phase_incr_two                      : integer := 57
+        phase_incr_two                      : integer := 57;
+        sampling_f					: integer := 4535;	-- 100MHz/22050Hz
+	    clock_cnt_width				: integer := 13
     );
     end sin_gen_sum_tb;
 
 
+
+
 --define inside of the module
 architecture behavioral of sin_gen_sum_tb is
 
-	--signals
+	    --define inside use signals
-		--signals
+        signal signal_f_one                   : std_Logic_vector(data_width - 1 downto 0) := (others => '0');
+        signal signal_f_two                   : std_Logic_vector(data_width - 1 downto 0) := (others => '0');
         signal clk 									: std_logic := '0';	--100mhz clock
         signal rst									: std_logic := '0';	--rst
         signal signal_out							: std_Logic_vector(data_width - 1 downto 0) := (others => '0');
+	    signal clk_22050                      : std_Logic := '0'; 
 
     --define components to use
     component sin_gen_sum is
         generic
         (
             phase_width 						: integer := 9;
-            data_width							: integer := 16;
+            data_width							: integer := 16
-            phase_incr_one                      : integer := phase_incr_one;
-            phase_incr_two                      : integer := phase_incr_two
         );
         port
         (
             clk 								: in std_logic;	--100mhz clock
-            rst									: in std_logic;	--rst
+            --rst									: in std_logic;	--rst
+            signal_in_one                       : in std_Logic_vector(data_width - 1 downto 0);
+            signal_in_two                       : in std_Logic_vector(data_width - 1 downto 0);
             signal_out							: out std_Logic_vector(data_width - 1 downto 0)--;
-            --fs_out							: in std_logic
         );
     end component;
 
+	component sin_gen is
+        generic
+        (
+            phase_width                 : integer := 9;
+            data_width                  : integer := 16;
+            
+            sampling_f					: integer := 4535;	-- 100MHz/22050Hz
+	        clock_cnt_width				: integer := 13
+        );
+        port
+        (
+            clk                         : in std_logic;	--100mhz clock
+            rst                         : in std_logic;	--rst
+            phase_incr                  : in std_Logic_vector(phase_width - 1 downto 0); --"frequency"
+            phase_out                   : out std_Logic_vector(phase_width - 1 downto 0);
+            signal_out                  : out std_Logic_vector(data_width - 1 downto 0);
+            fs_out                      : out std_logic --output sampling clock 22050Hz
+        );
+        end component;
+
+
+
+
     constant clk_period : time := 10 ns;
 
     begin    
     clk <= not clk after clk_period/2;
 	
-	uut : sin_gen_sum 
+
-	generic map
+uut  : sin_gen_sum   -- signal sumator
-	(
+    generic map
-		phase_width 				=> phase_width,
+    (
-        	data_width				=> data_width,
+        phase_width 						=> phase_width,
-        	phase_incr_one                      	=> phase_incr_one,
+        data_width						=> data_width
-        	phase_incr_two                      	=> phase_incr_two
+    )
-	)
+    port map
-	port map
+    (
-	(
+        clk 							    => clk,
-		clk 								=> clk,
+        --rst									=> rst,
-		rst								=> rst,
+        signal_in_one						=> signal_f_one,
-		signal_out							=> signal_out
+        signal_in_two						=> signal_f_two,
-	);
+        signal_out						=> signal_out
+    );
+
+sin_gen_one : sin_gen   -- first signal generator
+generic map
+(
+    phase_width 						=> phase_width,
+    data_width							=> data_width,
+    sampling_f							=> sampling_f,
+	 clock_cnt_width					=> clock_cnt_width
+)
+port map
+(
+    clk                          => clk,
+    rst									=> rst,
+    phase_incr							=> std_logic_Vector(To_unsigned(phase_incr_one,phase_width)),
+    --phase_out						        => phase_out,
+    signal_out							=> signal_f_one,
+	fs_out								=> clk_22050
+);
+
+sin_gen_two : sin_gen   -- second signal generator
+generic map
+(
+    phase_width 						=> phase_width,
+    data_width							=> data_width,
+    sampling_f							=> sampling_f,
+	 clock_cnt_width						=> clock_cnt_width
+)
+port map
+(
+    clk 							    => clk,
+    rst									=> rst,
+    phase_incr							=> std_logic_Vector(To_unsigned(phase_incr_two,phase_width)),
+    --phase_out					        	=> phase_out,
+    signal_out							=> signal_f_two
+);
 
     --tb process
     process
@@ -87,6 +151,4 @@ architecture behavioral of sin_gen_sum_tb is
 	wait;
 	end process;
 
-
-
 end behavioral;