diff --git a/ld3/dds_vhdl/fir.qip b/ld3/dds_vhdl/fir.qip index 89e45e4..98ba47d 100644 --- a/ld3/dds_vhdl/fir.qip +++ b/ld3/dds_vhdl/fir.qip @@ -26,9 +26,9 @@ set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAM set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "c3ltbWV0cnlNb2Rl::bnN5bQ==::U3ltbWV0cnk=" set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "TF9iYW5kc0ZpbHRlcg==::MQ==::TC10aCBCYW5kIEZpbHRlcg==" set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "aW5wdXRDaGFubmVsTnVt::MQ==::TWF4IE51bWJlciBvZiBDaGFubmVscw==" -set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y2xvY2tSYXRl::MTAw::Q2xvY2sgUmF0ZQ==" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y2xvY2tSYXRl::MC4wMjIwNQ==::Q2xvY2sgUmF0ZQ==" set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y2xvY2tTbGFjaw==::MA==::Q2xvY2sgU2xhY2s=" -set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "aW5wdXRSYXRl::MTAw::SW5wdXQgU2FtcGxlIFJhdGUgKE1TUFMp" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "aW5wdXRSYXRl::MC4wMjIwNQ==::SW5wdXQgU2FtcGxlIFJhdGUgKE1TUFMp" set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y29lZmZSZWxvYWQ=::ZmFsc2U=::Q29lZmZpY2llbnRzIFJlbG9hZA==" set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y29lZmZpY2llbnRSZWFkYmFjaw==::ZmFsc2U=::Y29lZmZpY2llbnRSZWFkYmFjaw==" set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y29lZmZpY2llbnRXcml0ZWFibGU=::ZmFsc2U=::Y29lZmZpY2llbnRXcml0ZWFibGU=" diff --git a/ld3/dds_vhdl/fir.vhd b/ld3/dds_vhdl/fir.vhd index 96df429..780bb6d 100644 --- a/ld3/dds_vhdl/fir.vhd +++ b/ld3/dds_vhdl/fir.vhd @@ -83,9 +83,9 @@ end architecture rtl; -- of fir -- Retrieval info: -- Retrieval info: -- Retrieval info: --- Retrieval info: +-- Retrieval info: -- Retrieval info: --- Retrieval info: +-- Retrieval info: -- Retrieval info: -- Retrieval info: -- Retrieval info: diff --git a/ld3/dds_vhdl/fir/fir_0002_rtl_core.vhd b/ld3/dds_vhdl/fir/fir_0002_rtl_core.vhd index ef1793c..73142d5 100644 --- a/ld3/dds_vhdl/fir/fir_0002_rtl_core.vhd +++ b/ld3/dds_vhdl/fir/fir_0002_rtl_core.vhd @@ -16,7 +16,7 @@ -- --------------------------------------------------------------------------- -- VHDL created from fir_0002_rtl_core --- VHDL created on Tue Jun 09 18:16:08 2020 +-- VHDL created on Wed Jun 10 17:16:42 2020 library IEEE; diff --git a/ld3/dds_vhdl/fir_sim/aldec/rivierapro_setup.tcl b/ld3/dds_vhdl/fir_sim/aldec/rivierapro_setup.tcl index 04dced2..6bcb25a 100644 --- a/ld3/dds_vhdl/fir_sim/aldec/rivierapro_setup.tcl +++ b/ld3/dds_vhdl/fir_sim/aldec/rivierapro_setup.tcl @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 19.1 670 win32 2020.06.09.18:16:15 +# ACDS 19.1 670 win32 2020.06.10.17:16:48 # ---------------------------------------- # Auto-generated simulation script rivierapro_setup.tcl # ---------------------------------------- diff --git a/ld3/dds_vhdl/fir_sim/cadence/ncsim_setup.sh b/ld3/dds_vhdl/fir_sim/cadence/ncsim_setup.sh index 4f77fc7..b8743fd 100644 --- a/ld3/dds_vhdl/fir_sim/cadence/ncsim_setup.sh +++ b/ld3/dds_vhdl/fir_sim/cadence/ncsim_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 19.1 670 win32 2020.06.09.18:16:15 +# ACDS 19.1 670 win32 2020.06.10.17:16:48 # ---------------------------------------- # ncsim - auto-generated simulation script @@ -106,7 +106,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 19.1 670 win32 2020.06.09.18:16:15 +# ACDS 19.1 670 win32 2020.06.10.17:16:48 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="fir" diff --git a/ld3/dds_vhdl/fir_sim/fir_input.txt b/ld3/dds_vhdl/fir_sim/fir_input.txt index d388698..2dab4a4 100644 --- a/ld3/dds_vhdl/fir_sim/fir_input.txt +++ b/ld3/dds_vhdl/fir_sim/fir_input.txt @@ -81,47 +81,47 @@ 0 0 0 --6804 --7424 --9673 -11030 --17117 -13591 --31248 -14940 --21868 --17002 --15878 --7873 --18900 --9386 --14628 -32567 -4720 --19739 --13837 -12911 -16220 --18003 --2374 -3596 -24737 --4863 --24276 -20032 -31499 -14450 -98 -9422 -25309 --10432 --29523 --30326 --28282 --18678 --10718 -14639 -26177 +10987 +-13679 +-16074 +-30691 +3112 +16798 +-1713 +-25728 +-8040 +-9094 +-24258 +-5223 +20803 +16580 +8315 +32333 +-1475 +31169 +31412 +81 +-4422 +-16781 +12806 +21929 +-3569 +-19942 +-21913 +15493 +22121 +15586 +21871 +2677 +-24068 +-30569 +13816 +18877 +13314 +-21445 +11509 +-22882 +-24684 0 0 0 diff --git a/ld3/dds_vhdl/fir_sim/fir_model.m b/ld3/dds_vhdl/fir_sim/fir_model.m index e67f916..4341f18 100644 --- a/ld3/dds_vhdl/fir_sim/fir_model.m +++ b/ld3/dds_vhdl/fir_sim/fir_model.m @@ -19,7 +19,7 @@ % their respective licensors. No other licenses, including any licenses % needed under any third party's intellectual property, are provided herein. % ================================================================================ -% Generated on: 06/09/2020 18:16:10 +% Generated on: 06/10/2020 17:16:45 % Generated by: FIR Compiler II 19.1 %--------------------------------------------------------------------------------------------------------- % diff --git a/ld3/dds_vhdl/fir_sim/fir_param.txt b/ld3/dds_vhdl/fir_sim/fir_param.txt index 0b9c6e9..62ed346 100644 --- a/ld3/dds_vhdl/fir_sim/fir_param.txt +++ b/ld3/dds_vhdl/fir_sim/fir_param.txt @@ -10,8 +10,8 @@ OutFracWidth : 28 OutFullFracWidth : 28 nChans : 41 nTaps : 41 -clockRate : 100 -inRate : 100 +clockRate : 0.02205 +inRate : 0.02205 interpN : 1 decimN : 1 busDataWidth : 16 diff --git a/ld3/dds_vhdl/fir_sim/fir_rtl_core.vhd b/ld3/dds_vhdl/fir_sim/fir_rtl_core.vhd index 99d5815..8570258 100644 --- a/ld3/dds_vhdl/fir_sim/fir_rtl_core.vhd +++ b/ld3/dds_vhdl/fir_sim/fir_rtl_core.vhd @@ -16,7 +16,7 @@ -- --------------------------------------------------------------------------- -- VHDL created from fir_rtl_core --- VHDL created on Tue Jun 09 18:16:09 2020 +-- VHDL created on Wed Jun 10 17:16:42 2020 library IEEE; diff --git a/ld3/dds_vhdl/fir_sim/mentor/msim_setup.tcl b/ld3/dds_vhdl/fir_sim/mentor/msim_setup.tcl index de546e8..a22c5fe 100644 --- a/ld3/dds_vhdl/fir_sim/mentor/msim_setup.tcl +++ b/ld3/dds_vhdl/fir_sim/mentor/msim_setup.tcl @@ -94,7 +94,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 19.1 670 win32 2020.06.09.18:16:15 +# ACDS 19.1 670 win32 2020.06.10.17:16:48 # ---------------------------------------- # Initialize variables diff --git a/ld3/dds_vhdl/fir_sim/synopsys/vcsmx/vcsmx_setup.sh b/ld3/dds_vhdl/fir_sim/synopsys/vcsmx/vcsmx_setup.sh index 2b0d24a..98dadf6 100644 --- a/ld3/dds_vhdl/fir_sim/synopsys/vcsmx/vcsmx_setup.sh +++ b/ld3/dds_vhdl/fir_sim/synopsys/vcsmx/vcsmx_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 19.1 670 win32 2020.06.09.18:16:15 +# ACDS 19.1 670 win32 2020.06.10.17:16:48 # ---------------------------------------- # vcsmx - auto-generated simulation script @@ -107,7 +107,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 19.1 670 win32 2020.06.09.18:16:15 +# ACDS 19.1 670 win32 2020.06.10.17:16:48 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="fir" diff --git a/ld3/dds_vhdl/lab3.vhd b/ld3/dds_vhdl/lab3.vhd index 2bbaf68..51d7d3f 100644 --- a/ld3/dds_vhdl/lab3.vhd +++ b/ld3/dds_vhdl/lab3.vhd @@ -28,8 +28,8 @@ entity lab3 is ( phase_width : integer := 9; data_width : integer := 16; - phase_incr_one : integer := 37; -- 22050/1664 - phase_incr_two : integer := 57; + phase_incr_one : integer := 37; -- Ph_inc = (f_out * 2^(B_n))/f_clk + phase_incr_two : integer := 57; -- 2496 * 2^9 / 22050 sampling_f : integer := 4535; -- 100MHz/22050 clock_cnt_width : integer := 13 ); @@ -45,8 +45,9 @@ architecture behavioral of lab3 is --define inside use signals signal signal_f_one : std_Logic_vector(data_width - 1 downto 0) := (others => '0'); signal signal_f_two : std_Logic_vector(data_width - 1 downto 0) := (others => '0'); - signal signal_sum : std_Logic_vector(data_width - 1 downto 0) := (others => '0'); - signal clk_22050 : std_Logic := '0'; + signal signal_sum : std_Logic_vector(data_width - 1 downto 0) := (others => '0'); + signal clk_22050 : std_Logic := '0'; + signal not_rst : std_Logic := '1'; --define components to use component sin_gen is @@ -111,6 +112,9 @@ architecture behavioral of lab3 is begin --define the operation of the module! +not_rst <= std_logic(not rst); + + sin_gen_one : sin_gen -- first signal generator generic map ( @@ -176,14 +180,14 @@ port map fir_one : fir -- FIR filter from Altera Megawizard plugin IP Core port map ( - clk => clk, -- clk.clk - reset_n => rst, -- rst.reset_n - ast_sink_data => signal_sum,-- avalon_streaming_sink.data - ast_sink_valid => '1', -- .valid - ast_sink_error => "00" -- .error - -- ast_source_data => -- avalon_streaming_source.data - -- ast_source_valid => -- .valid - -- ast_source_error => -- .error + clk => clk_22050, -- clk.clk + reset_n => not_rst, -- rst.reset_n + ast_sink_data => signal_sum, -- avalon_streaming_sink.data + ast_sink_valid => '1', -- .valid + ast_sink_error => "00" -- .error (00: No error) + -- ast_source_data => -- avalon_streaming_source.data + -- ast_source_valid => -- .valid + -- ast_source_error => -- .error ); diff --git a/ld3/dds_vhdl/sin_gen.qsf b/ld3/dds_vhdl/sin_gen.qsf index d34f4a3..c54657d 100644 --- a/ld3/dds_vhdl/sin_gen.qsf +++ b/ld3/dds_vhdl/sin_gen.qsf @@ -39,7 +39,7 @@ set_global_assignment -name FAMILY "Cyclone V" set_global_assignment -name DEVICE 5CGXFC7C7F23C8 -set_global_assignment -name TOP_LEVEL_ENTITY lab3 +set_global_assignment -name TOP_LEVEL_ENTITY sin_gen_sum set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:16:23 MARCH 21, 2018" set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition" @@ -54,12 +54,10 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name VHDL_FILE lab3_tb.vhd -set_global_assignment -name VHDL_FILE lab3.vhd set_global_assignment -name VHDL_FILE sin_gen_sum_tb.vhd set_global_assignment -name VHDL_FILE sin_gen_sum.vhd set_global_assignment -name VHDL_FILE sin_gen_tb.vhd set_global_assignment -name VHDL_FILE sin_gen.vhd +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_global_assignment -name QIP_FILE fir.qip -set_global_assignment -name SIP_FILE fir.sip -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +set_global_assignment -name SIP_FILE fir.sip \ No newline at end of file diff --git a/ld3/dds_vhdl/sin_gen.vhd b/ld3/dds_vhdl/sin_gen.vhd index d78d4ba..e153478 100644 --- a/ld3/dds_vhdl/sin_gen.vhd +++ b/ld3/dds_vhdl/sin_gen.vhd @@ -22,7 +22,7 @@ use ieee.numeric_std.all; --use this library if arithmetic required entity sin_gen is generic ( - phase_width : integer := 9; + phase_width : integer := 9; data_width : integer := 16; sampling_f : integer := 4535; -- 100MHz/22050 clock_cnt_width : integer := 13 @@ -585,9 +585,9 @@ begin --define the operation of the module! else if clock_cnt <= sampling_f then clock_cnt <= unsigned(clock_cnt) + 1; - if clock_cnt = (sampling_f-1)/2 then - clock_out <= not clock_out; - end if; + --if clock_cnt = (sampling_f-1)/2 then + -- clock_out <= not clock_out; + --end if; else phase_cnt <= unsigned(phase_cnt) + unsigned(phase_incr); clock_cnt <= (others => '0'); diff --git a/ld3/dds_vhdl/sin_gen_sum.vhd b/ld3/dds_vhdl/sin_gen_sum.vhd index 4eba60d..7960e8e 100644 --- a/ld3/dds_vhdl/sin_gen_sum.vhd +++ b/ld3/dds_vhdl/sin_gen_sum.vhd @@ -26,9 +26,7 @@ entity sin_gen_sum is generic ( phase_width : integer := 9; - data_width : integer := 16--; - --phase_incr_one : integer := 37; - --phase_incr_two : integer := 57 + data_width : integer := 16 ); port ( @@ -42,66 +40,15 @@ entity sin_gen_sum is --define inside of the module architecture behavioral of sin_gen_sum is - --define inside use signals - --signal signal_out_one : std_Logic_vector(data_width - 1 downto 0) := (others => '0'); - --signal signal_out_two : std_Logic_vector(data_width - 1 downto 0) := (others => '0'); - signal signal_summ : signed(data_width - 1 downto 0) := (others => '0'); -- 16bit word + + signal signal_summ : signed(data_width - 1 downto 0) := (others => '0'); -- 16bit word - --define components to use - -- component sin_gen is - -- generic - -- ( - -- phase_width : integer := 9; - -- data_width : integer := 16 - -- ); - -- port - -- ( - -- clk : in std_logic; --100mhz clock - -- rst : in std_logic; --rst - -- --phase_incr : in std_Logic_vector(phase_width - 1 downto 0); --"frequency" - -- signal_f_one : out std_Logic_vector(data_width - 1 downto 0); -- - -- signal_f_two : out std_Logic_vector(data_width - 1 downto 0); - -- --phase_out : out std_Logic_vector(phase_width - 1 downto 0); - -- signal_out : out std_Logic_vector(data_width - 1 downto 0) - -- ); - -- end component; begin --define the operation of the module! --signal output signal_out <= std_logic_Vector(signal_summ); - --- sin_gen_one : sin_gen --- generic map --- ( --- phase_width => phase_width, --- data_width => data_width --- ) --- port map --- ( --- clk => clk, --- rst => rst, --- phase_incr => std_logic_Vector(To_unsigned(phase_incr_one,phase_width)), --- --phase_out => phase_out, --- signal_out => signal_out_one --- ); - --- sin_gen_two : sin_gen --- generic map --- ( --- phase_width => phase_width, --- data_width => data_width --- ) --- port map --- ( --- clk => clk, --- rst => rst, --- phase_incr => std_logic_Vector(To_unsigned(phase_incr_two,phase_width)), --- --phase_out => phase_out, --- signal_out => signal_out_two --- ); - --adder process(clk) begin diff --git a/ld3/dds_vhdl/sin_gen_sum_tb.vhd b/ld3/dds_vhdl/sin_gen_sum_tb.vhd index 0286cad..06b5167 100644 --- a/ld3/dds_vhdl/sin_gen_sum_tb.vhd +++ b/ld3/dds_vhdl/sin_gen_sum_tb.vhd @@ -1,92 +1,154 @@ ------------------------------ --- Author Imants Pulkstenis --- Date 09.06.2020 --- Project name Labwork No3 --- Module name sin_gen_sum_tb --- --- Detailed module description --- Test bench for signal sum module --- --- --- Revision: --- A - initial design --- B - --- ------------------------------ -library ieee; --always use this library -use ieee.std_logic_1164.all; --always use this library - -use ieee.numeric_std.all; --use this library if arithmetic required - ---define connections to outside -entity sin_gen_sum_tb is - generic - ( - phase_width : integer := 9; - data_width : integer := 16; - phase_incr_one : integer := 37; - phase_incr_two : integer := 57 - ); - end sin_gen_sum_tb; - - ---define inside of the module -architecture behavioral of sin_gen_sum_tb is - - --signals - --signals - signal clk : std_logic := '0'; --100mhz clock - signal rst : std_logic := '0'; --rst - signal signal_out : std_Logic_vector(data_width - 1 downto 0) := (others => '0'); - - --define components to use - component sin_gen_sum is - generic - ( - phase_width : integer := 9; - data_width : integer := 16; - phase_incr_one : integer := phase_incr_one; - phase_incr_two : integer := phase_incr_two - ); - port - ( - clk : in std_logic; --100mhz clock - rst : in std_logic; --rst - signal_out : out std_Logic_vector(data_width - 1 downto 0)--; - --fs_out : in std_logic - ); - end component; - - constant clk_period : time := 10 ns; - - begin - clk <= not clk after clk_period/2; - - uut : sin_gen_sum - generic map - ( - phase_width => phase_width, - data_width => data_width, - phase_incr_one => phase_incr_one, - phase_incr_two => phase_incr_two - ) - port map - ( - clk => clk, - rst => rst, - signal_out => signal_out - ); - - --tb process - process - begin - rst <= '1'; - wait for 100 ns; - rst <= '0'; - - wait; - end process; - - - +----------------------------- +-- Author Imants Pulkstenis +-- Date 09.06.2020 +-- Project name Labwork No3 +-- Module name sin_gen_sum_tb +-- +-- Detailed module description +-- Test bench for signal sum module +-- +-- +-- Revision: +-- A - initial design +-- B - Remove sin_gen module out of this module +-- +----------------------------- +library ieee; --always use this library +use ieee.std_logic_1164.all; --always use this library + +use ieee.numeric_std.all; --use this library if arithmetic required + +--define connections to outside +entity sin_gen_sum_tb is + generic + ( + phase_width : integer := 9; + data_width : integer := 16; + phase_incr_one : integer := 37; + phase_incr_two : integer := 57; + sampling_f : integer := 4535; -- 100MHz/22050Hz + clock_cnt_width : integer := 13 + ); + end sin_gen_sum_tb; + + + + +--define inside of the module +architecture behavioral of sin_gen_sum_tb is + + --define inside use signals + signal signal_f_one : std_Logic_vector(data_width - 1 downto 0) := (others => '0'); + signal signal_f_two : std_Logic_vector(data_width - 1 downto 0) := (others => '0'); + signal clk : std_logic := '0'; --100mhz clock + signal rst : std_logic := '0'; --rst + signal signal_out : std_Logic_vector(data_width - 1 downto 0) := (others => '0'); + signal clk_22050 : std_Logic := '0'; + + --define components to use + component sin_gen_sum is + generic + ( + phase_width : integer := 9; + data_width : integer := 16 + ); + port + ( + clk : in std_logic; --100mhz clock + --rst : in std_logic; --rst + signal_in_one : in std_Logic_vector(data_width - 1 downto 0); + signal_in_two : in std_Logic_vector(data_width - 1 downto 0); + signal_out : out std_Logic_vector(data_width - 1 downto 0)--; + ); + end component; + + component sin_gen is + generic + ( + phase_width : integer := 9; + data_width : integer := 16; + + sampling_f : integer := 4535; -- 100MHz/22050Hz + clock_cnt_width : integer := 13 + ); + port + ( + clk : in std_logic; --100mhz clock + rst : in std_logic; --rst + phase_incr : in std_Logic_vector(phase_width - 1 downto 0); --"frequency" + phase_out : out std_Logic_vector(phase_width - 1 downto 0); + signal_out : out std_Logic_vector(data_width - 1 downto 0); + fs_out : out std_logic --output sampling clock 22050Hz + ); + end component; + + + + + constant clk_period : time := 10 ns; + + begin + clk <= not clk after clk_period/2; + + +uut : sin_gen_sum -- signal sumator + generic map + ( + phase_width => phase_width, + data_width => data_width + ) + port map + ( + clk => clk, + --rst => rst, + signal_in_one => signal_f_one, + signal_in_two => signal_f_two, + signal_out => signal_out + ); + +sin_gen_one : sin_gen -- first signal generator +generic map +( + phase_width => phase_width, + data_width => data_width, + sampling_f => sampling_f, + clock_cnt_width => clock_cnt_width +) +port map +( + clk => clk, + rst => rst, + phase_incr => std_logic_Vector(To_unsigned(phase_incr_one,phase_width)), + --phase_out => phase_out, + signal_out => signal_f_one, + fs_out => clk_22050 +); + +sin_gen_two : sin_gen -- second signal generator +generic map +( + phase_width => phase_width, + data_width => data_width, + sampling_f => sampling_f, + clock_cnt_width => clock_cnt_width +) +port map +( + clk => clk, + rst => rst, + phase_incr => std_logic_Vector(To_unsigned(phase_incr_two,phase_width)), + --phase_out => phase_out, + signal_out => signal_f_two +); + + --tb process + process + begin + rst <= '1'; + wait for 100 ns; + rst <= '0'; + + wait; + end process; + end behavioral; \ No newline at end of file