FIR and IIR filter and test benches are now working
This commit is contained in:
@@ -39,7 +39,7 @@
|
||||
|
||||
set_global_assignment -name FAMILY "Cyclone V"
|
||||
set_global_assignment -name DEVICE 5CGXFC7C7F23C8
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY lab3
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY sin_gen_sum
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:16:23 MARCH 21, 2018"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
|
||||
@@ -54,12 +54,10 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name VHDL_FILE lab3_tb.vhd
|
||||
set_global_assignment -name VHDL_FILE lab3.vhd
|
||||
set_global_assignment -name VHDL_FILE sin_gen_sum_tb.vhd
|
||||
set_global_assignment -name VHDL_FILE sin_gen_sum.vhd
|
||||
set_global_assignment -name VHDL_FILE sin_gen_tb.vhd
|
||||
set_global_assignment -name VHDL_FILE sin_gen.vhd
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
set_global_assignment -name QIP_FILE fir.qip
|
||||
set_global_assignment -name SIP_FILE fir.sip
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
set_global_assignment -name SIP_FILE fir.sip
|
||||
Reference in New Issue
Block a user