FIR and IIR filter and test benches are now working

ld3/dds_vhdl/fir_sim/aldec/rivierapro_setup.tcl

@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 19.1 670 win32 2020.06.09.18:16:15
+# ACDS 19.1 670 win32 2020.06.10.17:16:48
 # ----------------------------------------
 # Auto-generated simulation script rivierapro_setup.tcl
 # ----------------------------------------

ld3/dds_vhdl/fir_sim/cadence/ncsim_setup.sh

@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 19.1 670 win32 2020.06.09.18:16:15
+# ACDS 19.1 670 win32 2020.06.10.17:16:48
 
 # ----------------------------------------
 # ncsim - auto-generated simulation script
@@ -106,7 +106,7 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 19.1 670 win32 2020.06.09.18:16:15
+# ACDS 19.1 670 win32 2020.06.10.17:16:48
 # ----------------------------------------
 # initialize variables
 TOP_LEVEL_NAME="fir"

ld3/dds_vhdl/fir_sim/fir_input.txt

@@ -81,47 +81,47 @@
 0 
 0 
 0 
--6804 
--7424 
--9673 
-11030 
--17117 
-13591 
--31248 
-14940 
--21868 
--17002 
--15878 
--7873 
--18900 
--9386 
--14628 
-32567 
-4720 
--19739 
--13837 
-12911 
-16220 
--18003 
--2374 
-3596 
-24737 
--4863 
--24276 
-20032 
-31499 
-14450 
-98 
-9422 
-25309 
--10432 
--29523 
--30326 
--28282 
--18678 
--10718 
-14639 
-26177 
+10987 
+-13679 
+-16074 
+-30691 
+3112 
+16798 
+-1713 
+-25728 
+-8040 
+-9094 
+-24258 
+-5223 
+20803 
+16580 
+8315 
+32333 
+-1475 
+31169 
+31412 
+81 
+-4422 
+-16781 
+12806 
+21929 
+-3569 
+-19942 
+-21913 
+15493 
+22121 
+15586 
+21871 
+2677 
+-24068 
+-30569 
+13816 
+18877 
+13314 
+-21445 
+11509 
+-22882 
+-24684 
 0 
 0 
 0 

ld3/dds_vhdl/fir_sim/fir_model.m

@@ -19,7 +19,7 @@
 % their respective licensors.  No other licenses, including any licenses
 % needed under any third party's intellectual property, are provided herein.
 % ================================================================================
-% Generated on: 06/09/2020 18:16:10
+% Generated on: 06/10/2020 17:16:45
 % Generated by: FIR Compiler II 19.1
 %---------------------------------------------------------------------------------------------------------
 %

ld3/dds_vhdl/fir_sim/fir_param.txt

@@ -10,8 +10,8 @@ OutFracWidth : 28
 OutFullFracWidth : 28 
 nChans : 41 
 nTaps : 41 
-clockRate : 100 
-inRate : 100 
+clockRate : 0.02205 
+inRate : 0.02205 
 interpN : 1 
 decimN : 1 
 busDataWidth : 16 

ld3/dds_vhdl/fir_sim/fir_rtl_core.vhd

@@ -16,7 +16,7 @@
 -- ---------------------------------------------------------------------------
 
 -- VHDL created from fir_rtl_core
--- VHDL created on Tue Jun 09 18:16:09 2020
+-- VHDL created on Wed Jun 10 17:16:42 2020
 
 
 library IEEE;

ld3/dds_vhdl/fir_sim/mentor/msim_setup.tcl

@@ -94,7 +94,7 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 19.1 670 win32 2020.06.09.18:16:15
+# ACDS 19.1 670 win32 2020.06.10.17:16:48
 
 # ----------------------------------------
 # Initialize variables

ld3/dds_vhdl/fir_sim/synopsys/vcsmx/vcsmx_setup.sh

@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 19.1 670 win32 2020.06.09.18:16:15
+# ACDS 19.1 670 win32 2020.06.10.17:16:48
 
 # ----------------------------------------
 # vcsmx - auto-generated simulation script
@@ -107,7 +107,7 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 19.1 670 win32 2020.06.09.18:16:15
+# ACDS 19.1 670 win32 2020.06.10.17:16:48
 # ----------------------------------------
 # initialize variables
 TOP_LEVEL_NAME="fir"