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Timming now correct and also

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7-segmet display also working now
This commit is contained in:
Imants Pulkstenis
2020-04-12 22:44:24 +03:00
parent be0c2ab376
commit 9a6c90c0b2
7 changed files with 149 additions and 132 deletions
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ld2/7segment.v
+84 -92
View File
@@ -8,7 +8,7 @@
//
// This module 16bit input transforms
// in 7-segment display induvidual segments
// as outputs. Input clock is 10kHz and it
// as outputs. Input clock is 1kHz and it
// drives common anode for 7-segment display
//
//
@@ -19,7 +19,7 @@
//
/////////////////////////////
module bin_7segment(
input clk, // clock working with 10kHz
input clk, // clock working with 1kHz
input [15:0] in, // input
output [6:0] seg, // individual segments of number
output [3:0] an, // anode to select character
@@ -34,7 +34,8 @@ parameter [SIZE-1:0] ONE = 2'b00,
FOUR = 2'b11;
reg [SIZE-1:0] state=ONE, next=TWO;
reg [3:0] nibble = 'b0 ;
reg [6:0] r_nibble = 'b0 ;
reg [3:0] r_an = 'b0 ;
//---------State register sequential always block-----------
always @(posedge clk ) begin
@@ -45,107 +46,98 @@ end
always@(posedge clk)begin
case(state)
ONE : begin
next <= TWO;
nibble <= in[3:0];
next <= TWO;
r_an <= 4'b0001;
case (in[3:0])
4'h0 : r_nibble <= 7'b0111111;
4'h1 : r_nibble <= 7'b0000110;
4'h2 : r_nibble <= 7'b1011011;
4'h3 : r_nibble <= 7'b1001111;
4'h4 : r_nibble <= 7'b1100110;
4'h5 : r_nibble <= 7'b1101101;
4'h6 : r_nibble <= 7'b1111101;
4'h7 : r_nibble <= 7'b0000111;
4'h8 : r_nibble <= 7'b1111111;
4'h9 : r_nibble <= 7'b1101111;
4'ha : r_nibble <= 7'b1110111;
4'hb : r_nibble <= 7'b1111100;
4'hc : r_nibble <= 7'b0111001;
4'hd : r_nibble <= 7'b1011110;
4'he : r_nibble <= 7'b1111001;
4'hf : r_nibble <= 7'b1110001;
endcase
end
TWO : begin
next <= THREE;
nibble <= in[7:4];
r_an <= 4'b0010;
case (in[7:4])
4'h0 : r_nibble <= 7'b0111111;
4'h1 : r_nibble <= 7'b0000110;
4'h2 : r_nibble <= 7'b1011011;
4'h3 : r_nibble <= 7'b1001111;
4'h4 : r_nibble <= 7'b1100110;
4'h5 : r_nibble <= 7'b1101101;
4'h6 : r_nibble <= 7'b1111101;
4'h7 : r_nibble <= 7'b0000111;
4'h8 : r_nibble <= 7'b1111111;
4'h9 : r_nibble <= 7'b1101111;
4'ha : r_nibble <= 7'b1110111;
4'hb : r_nibble <= 7'b1111100;
4'hc : r_nibble <= 7'b0111001;
4'hd : r_nibble <= 7'b1011110;
4'he : r_nibble <= 7'b1111001;
4'hf : r_nibble <= 7'b1110001;
endcase
end
THREE : begin
next <= FOUR;
nibble <= in[11:8];
r_an <= 4'b0100;
case (in[11:8])
4'h0 : r_nibble <= 7'b0111111;
4'h1 : r_nibble <= 7'b0000110;
4'h2 : r_nibble <= 7'b1011011;
4'h3 : r_nibble <= 7'b1001111;
4'h4 : r_nibble <= 7'b1100110;
4'h5 : r_nibble <= 7'b1101101;
4'h6 : r_nibble <= 7'b1111101;
4'h7 : r_nibble <= 7'b0000111;
4'h8 : r_nibble <= 7'b1111111;
4'h9 : r_nibble <= 7'b1101111;
4'ha : r_nibble <= 7'b1110111;
4'hb : r_nibble <= 7'b1111100;
4'hc : r_nibble <= 7'b0111001;
4'hd : r_nibble <= 7'b1011110;
4'he : r_nibble <= 7'b1111001;
4'hf : r_nibble <= 7'b1110001;
endcase
end
FOUR : begin
next <= ONE;
nibble <= in[15:12];
r_an <= 4'b1000;
case (in[15:12])
4'h0 : r_nibble <= 7'b0111111;
4'h1 : r_nibble <= 7'b0000110;
4'h2 : r_nibble <= 7'b1011011;
4'h3 : r_nibble <= 7'b1001111;
4'h4 : r_nibble <= 7'b1100110;
4'h5 : r_nibble <= 7'b1101101;
4'h6 : r_nibble <= 7'b1111101;
4'h7 : r_nibble <= 7'b0000111;
4'h8 : r_nibble <= 7'b1111111;
4'h9 : r_nibble <= 7'b1101111;
4'ha : r_nibble <= 7'b1110111;
4'hb : r_nibble <= 7'b1111100;
4'hc : r_nibble <= 7'b0111001;
4'hd : r_nibble <= 7'b1011110;
4'he : r_nibble <= 7'b1111001;
4'hf : r_nibble <= 7'b1110001;
endcase
end
endcase
end
assign seg[6] = ( nibble == 4'h2 ||
nibble == 4'h3 ||
nibble == 4'h4 ||
nibble == 4'h5 ||
nibble == 4'h6 ||
nibble == 4'h8 ||
nibble == 4'h9 ||
nibble == 4'hA ||
nibble == 4'hB ||
nibble == 4'hD ||
nibble == 4'hE ||
nibble == 4'hF ) ? 1'b0 : 1'b1;
assign seg[5] = ( nibble == 4'h0 ||
nibble == 4'h4 ||
nibble == 4'h5 ||
nibble == 4'h6 ||
nibble == 4'h8 ||
nibble == 4'h9 ||
nibble == 4'hA ||
nibble == 4'hB ||
nibble == 4'hC ||
nibble == 4'hE ||
nibble == 4'hF ) ? 1'b0 : 1'b1;
assign seg[4] = ( nibble == 4'h0 ||
nibble == 4'h2 ||
nibble == 4'h6 ||
nibble == 4'h8 ||
nibble == 4'hA ||
nibble == 4'hB ||
nibble == 4'hC ||
nibble == 4'hD ||
nibble == 4'hE ||
nibble == 4'hF ) ? 1'b0 : 1'b1;
assign seg[3] = ( nibble == 4'h0 ||
nibble == 4'h2 ||
nibble == 4'h3 ||
nibble == 4'h5 ||
nibble == 4'h6 ||
nibble == 4'h8 ||
nibble == 4'h9 ||
nibble == 4'hB ||
nibble == 4'hC ||
nibble == 4'hD ||
nibble == 4'hE ) ? 1'b0 : 1'b1;
assign seg[2] = ( nibble == 4'h0 ||
nibble == 4'h1 ||
nibble == 4'h3 ||
nibble == 4'h4 ||
nibble == 4'h5 ||
nibble == 4'h6 ||
nibble == 4'h7 ||
nibble == 4'h8 ||
nibble == 4'h9 ||
nibble == 4'hA ||
nibble == 4'hB ||
nibble == 4'hD ) ? 1'b0 : 1'b1;
assign seg[1] = ( nibble == 4'h0 ||
nibble == 4'h1 ||
nibble == 4'h2 ||
nibble == 4'h3 ||
nibble == 4'h4 ||
nibble == 4'h7 ||
nibble == 4'h8 ||
nibble == 4'h9 ||
nibble == 4'hA ||
nibble == 4'hD ) ? 1'b0 : 1'b1;
assign seg[0] = ( nibble == 4'h0 ||
nibble == 4'h2 ||
nibble == 4'h3 ||
nibble == 4'h5 ||
nibble == 4'h6 ||
nibble == 4'h7 ||
nibble == 4'h8 ||
nibble == 4'h9 ||
nibble == 4'hA ||
nibble == 4'hC ||
nibble == 4'hE ||
nibble == 4'hF) ? 1'b0 : 1'b1;
assign dp = 1'b1; //dot
assign an[0] = (state==ONE) ? 1'b0 : 1'b1;
assign an[1] = (state==TWO) ? 1'b0 : 1'b1;
assign an[2] = (state==THREE) ? 1'b0 : 1'b1;
assign an[3] = (state==FOUR) ? 1'b0 : 1'b1;
assign seg = ~r_nibble; // inverse active LOW
assign dp = 1'b1; //dot
assign an = ~r_an; // inverse active LOW
endmodule
ld2/Basys3_Master.xdc
+24 -24
View File
@@ -21,30 +21,30 @@ set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
# set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
# set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
# set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
# set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
# set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
# set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
# set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
# set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
# set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
# set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
# set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
# set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
## LEDs
ld2/clock_divider_param.v → ld2/clock_divider.v
View File
ld2/clock_divider_param_tb.v → ld2/clock_divider_tb.v
+2 -2
View File
@@ -20,9 +20,9 @@
// `timescale [time unit] / [time precision]
`timescale 10 ps / 1 ps
`include "clock_divider_param.v"
`include "clock_divider.v"
module clock_divider_param_tb ();
module clock_divider_tb ();
reg clk = 1'b0;
wire enable;
ld2/counter.v
+12 -5
View File
@@ -20,19 +20,26 @@
module counter (
input clk,
input reset,
output [15:0] counter);
input [3:0] max,
output [15:0] counter);
always@(posedge clk) begin
if (reset == 'b1) begin
r_counter <= 'b0;
r_adder <= 'b0;
end
else begin
r_counter <= r_counter + 1;
if (r_adder >= max )begin
r_counter <= r_counter + 1;
r_adder <= 0;
end
else begin
r_adder <= r_adder + 1;
end
end
end
reg [15:0] r_counter = 'b0;
reg [15:0] r_adder = 'b0;
reg [15:0] r_counter = 'b0;
assign counter = r_counter;
ld2/top.v
+9 -7
View File
@@ -20,12 +20,12 @@
module top (
input clk,
output [15:0] led,
output [15:0] led,
// 7 segment
output [6:0] seg,
output [3:0] an,
output dp,
input [15:0] sw,
input [3:0] sw,
input btnC // reset
);
@@ -34,6 +34,7 @@ module top (
wire clk16Hz, clk1kHz, w_reset;
wire [15:0] w_counter;
//------assign outputs----------------------
assign led = w_counter;
@@ -42,11 +43,12 @@ assign led = w_counter;
counter counter(
.clk(clk16Hz),
.reset(w_reset),
.max(sw),
.counter(w_counter)
);
clock_divider #(
.DIVIDER(1_000),
.DIVIDER(50_000), // 50000 * 10ns = 500us
.WIDTH(24)
) clock_1kHz_gen (
.clk(clk),
@@ -54,8 +56,8 @@ clock_divider #(
);
clock_divider #(
.DIVIDER(5_000*625),
.WIDTH(22)
.DIVIDER(3_125_000), // 3125000 * 10ns = 31.25ms
.WIDTH(24)
) clock_16Hz_gen (
.clk(clk),
.clk_out(clk16Hz)
@@ -69,8 +71,8 @@ debounce_switch debounce_switch_reset(
);
bin_7segment bin_7segment(
.clk(clk1kHz), // clock working with 10kHz
.in(w_counter), // input
.clk(clk1kHz), // clock working with 10kHz
.in(w_counter), // input
.seg(seg), // individual segments of number
.an(an), // anode to select character
.dp(dp) // dot on 7segment display
ld2/top_tb.v
+18 -2
View File
@@ -25,7 +25,7 @@
`timescale 10 ns / 1ns
//sub modules
`include "clock_divider_param.v"
`include "clock_divider.v"
`include "7segment.v"
`include "debounce_switch.v"
`include "counter.v"
@@ -46,6 +46,7 @@ module top_tb#( parameter
reg clk = 1'b0;
reg reset = 1'b0;
reg [3:0] sw = 4'b0000;
// 50% duty cycle clock
always #0.5 clk <= ~clk;
@@ -56,7 +57,8 @@ wire RsTx;
top Test_Unit(
.clk(clk),
.btnC(reset)
.sw(sw),
.btnC(reset)
);
initial begin
@@ -84,6 +86,20 @@ initial begin
$display("*");
#1_000_000;
$display("*");
#1_000_000;
$display("*");
#1_000_000;
$display("*");
#1_000_000;
$display("*");
#1_000_000;
$display("*");
#1_000_000;
$display("*");
#1_000_000;
$display("*");
#1_000_000;
$display("*");
$display(" ");
$display("Use this command to open timing diagram:");
$display("gtkwave -f wave.vcd");