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Add files for FIR and IIR filter - not tested

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This commit is contained in:
Imants Pulkstenis
2020-06-09 22:28:53 +03:00
parent 01e4a4b6d3
commit 682207dfa1
66 changed files with 13930 additions and 43 deletions
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ld3/dds_vhdl/fir_sim/aldec/rivierapro_setup.tcl
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# (C) 2001-2020 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Altera
# Program License Subscription Agreement, Altera MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 19.1 670 win32 2020.06.09.18:16:15
# ----------------------------------------
# Auto-generated simulation script rivierapro_setup.tcl
# ----------------------------------------
# This script provides commands to simulate the following IP detected in
# your Quartus project:
# fir
#
# Altera recommends that you source this Quartus-generated IP simulation
# script from your own customized top-level script, and avoid editing this
# generated script.
#
# To write a top-level script that compiles Altera simulation libraries and
# the Quartus-generated IP in your project, along with your design and
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
# into a new file, e.g. named "aldec.do", and modify the text as directed.
#
# ----------------------------------------
# # TOP-LEVEL TEMPLATE - BEGIN
# #
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
# # construct paths to the files required to simulate the IP in your Quartus
# # project. By default, the IP script assumes that you are launching the
# # simulator from the IP script location. If launching from another
# # location, set QSYS_SIMDIR to the output directory you specified when you
# # generated the IP script, relative to the directory from which you launch
# # the simulator.
# #
# set QSYS_SIMDIR <script generation output directory>
# #
# # Source the generated IP simulation script.
# source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
# #
# # Set any compilation options you require (this is unusual).
# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
# #
# # Call command to compile the Quartus EDA simulation library.
# dev_com
# #
# # Call command to compile the Quartus-generated IP simulation files.
# com
# #
# # Add commands to compile all design files and testbench files, including
# # the top level. (These are all the files required for simulation other
# # than the files compiled by the Quartus-generated IP simulation script)
# #
# vlog -sv2k5 <your compilation options> <design and testbench files>
# #
# # Set the top-level simulation or testbench module/entity name, which is
# # used by the elab command to elaborate the top level.
# #
# set TOP_LEVEL_NAME <simulation top>
# #
# # Set any elaboration options you require.
# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
# #
# # Call command to elaborate your design and testbench.
# elab
# #
# # Run the simulation.
# run
# #
# # Report success to the shell.
# exit -code 0
# #
# # TOP-LEVEL TEMPLATE - END
# ----------------------------------------
#
# IP SIMULATION SCRIPT
# ----------------------------------------
# If fir is one of several IP cores in your
# Quartus project, you can generate a simulation script
# suitable for inclusion in your top-level simulation
# script by running the following command line:
#
# ip-setup-simulation --quartus-project=<quartus project>
#
# ip-setup-simulation will discover the Altera IP
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# ----------------------------------------
# Initialize variables
if ![info exists SYSTEM_INSTANCE_NAME] {
set SYSTEM_INSTANCE_NAME ""
} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
}
if ![info exists TOP_LEVEL_NAME] {
set TOP_LEVEL_NAME "fir"
}
if ![info exists QSYS_SIMDIR] {
set QSYS_SIMDIR "./../"
}
if ![info exists QUARTUS_INSTALL_DIR] {
set QUARTUS_INSTALL_DIR "C:/intelfpga_lite/19.1/quartus/"
}
if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
set USER_DEFINED_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_ELAB_OPTIONS] {
set USER_DEFINED_ELAB_OPTIONS ""
}
# ----------------------------------------
# Initialize simulation properties - DO NOT MODIFY!
set ELAB_OPTIONS ""
set SIM_OPTIONS ""
if ![ string match "*-64 vsim*" [ vsim -version ] ] {
} else {
}
set Aldec "Riviera"
if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
set Aldec "Active"
}
if { [ string match "Active" $Aldec ] } {
scripterconf -tcl
createdesign "$TOP_LEVEL_NAME" "."
opendesign "$TOP_LEVEL_NAME"
}
# ----------------------------------------
# Copy ROM/RAM files to simulation directory
alias file_copy {
echo "\[exec\] file_copy"
}
# ----------------------------------------
# Create compilation libraries
proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
ensure_lib ./libraries
ensure_lib ./libraries/work
vmap work ./libraries/work
ensure_lib ./libraries/altera_ver
vmap altera_ver ./libraries/altera_ver
ensure_lib ./libraries/lpm_ver
vmap lpm_ver ./libraries/lpm_ver
ensure_lib ./libraries/sgate_ver
vmap sgate_ver ./libraries/sgate_ver
ensure_lib ./libraries/altera_mf_ver
vmap altera_mf_ver ./libraries/altera_mf_ver
ensure_lib ./libraries/altera_lnsim_ver
vmap altera_lnsim_ver ./libraries/altera_lnsim_ver
ensure_lib ./libraries/cyclonev_ver
vmap cyclonev_ver ./libraries/cyclonev_ver
ensure_lib ./libraries/cyclonev_hssi_ver
vmap cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver
ensure_lib ./libraries/cyclonev_pcie_hip_ver
vmap cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver
ensure_lib ./libraries/altera
vmap altera ./libraries/altera
ensure_lib ./libraries/lpm
vmap lpm ./libraries/lpm
ensure_lib ./libraries/sgate
vmap sgate ./libraries/sgate
ensure_lib ./libraries/altera_mf
vmap altera_mf ./libraries/altera_mf
ensure_lib ./libraries/altera_lnsim
vmap altera_lnsim ./libraries/altera_lnsim
ensure_lib ./libraries/cyclonev
vmap cyclonev ./libraries/cyclonev
# ----------------------------------------
# Compile device library files
alias dev_com {
echo "\[exec\] dev_com"
eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf
vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_atoms_ncrypt.v" -work cyclonev
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd" -work cyclonev
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd" -work cyclonev
}
# ----------------------------------------
# Compile the design files in correct order
alias com {
echo "\[exec\] com"
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/dspba_library_package.vhd"
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/dspba_library.vhd"
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_math_pkg_hpfir.vhd"
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_lib_pkg_hpfir.vhd"
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_avalon_streaming_controller_hpfir.vhd"
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_avalon_streaming_sink_hpfir.vhd"
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_avalon_streaming_source_hpfir.vhd"
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_roundsat_hpfir.vhd"
eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_avalon_sc_fifo.v"
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/fir_rtl_core.vhd"
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/fir_ast.vhd"
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/fir.vhd"
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/fir_tb.vhd"
}
# ----------------------------------------
# Elaborate top level design
alias elab {
echo "\[exec\] elab"
eval vsim +access +r -t ps $ELAB_OPTIONS -L work -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev $TOP_LEVEL_NAME
}
# ----------------------------------------
# Elaborate the top level design with -dbg -O2 option
alias elab_debug {
echo "\[exec\] elab_debug"
eval vsim -dbg -O2 +access +r -t ps $ELAB_OPTIONS -L work -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev $TOP_LEVEL_NAME
}
# ----------------------------------------
# Compile all the design files and elaborate the top level design
alias ld "
dev_com
com
elab
"
# ----------------------------------------
# Compile all the design files and elaborate the top level design with -dbg -O2
alias ld_debug "
dev_com
com
elab_debug
"
# ----------------------------------------
# Print out user commmand line aliases
alias h {
echo "List Of Command Line Aliases"
echo
echo "file_copy -- Copy ROM/RAM files to simulation directory"
echo
echo "dev_com -- Compile device library files"
echo
echo "com -- Compile the design files in correct order"
echo
echo "elab -- Elaborate top level design"
echo
echo "elab_debug -- Elaborate the top level design with -dbg -O2 option"
echo
echo "ld -- Compile all the design files and elaborate the top level design"
echo
echo "ld_debug -- Compile all the design files and elaborate the top level design with -dbg -O2"
echo
echo
echo
echo "List Of Variables"
echo
echo "TOP_LEVEL_NAME -- Top level module name."
echo " For most designs, this should be overridden"
echo " to enable the elab/elab_debug aliases."
echo
echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
echo
echo "QSYS_SIMDIR -- Platform Designer base simulation directory."
echo
echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
echo
echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
echo
echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
echo
echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
echo
echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
}
file_copy
h
ld3/dds_vhdl/fir_sim/altera_avalon_sc_fifo.v
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// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
ld3/dds_vhdl/fir_sim/auk_dspip_avalon_streaming_controller_hpfir.vhd
+88
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@@ -0,0 +1,88 @@
-- (C) 2001-2019 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files from any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License Subscription
-- Agreement, Intel FPGA IP License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Intel and sold by
-- Intel or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------
-------------------------------------------------------------------------
--
-- $Revision: #1 $
-- $Date: 2009/07/29 $
-- Author : Boon Hong Oh
--
-- Project : Avalon Streaming Wrapper for HP FIR
--
-- Description :
--
-- This file is the Interface controller for the Avalon Streaming Wrapper.
-- The control signals between sink, core, and source modules are communicated
-- via the controller. The stall output is used as the core enable signal in
-- the wrapper.
--
-- ALTERA Confidential and Proprietary
-- Copyright 2006 (c) Altera Corporation
-- All rights reserved
--
-------------------------------------------------------------------------
-------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity auk_dspip_avalon_streaming_controller_hpfir is
port(
clk : in std_logic;
--clk_en : in std_logic := '1';
reset_n : in std_logic;
--ready : in std_logic;
sink_packet_error : in std_logic_vector (1 downto 0);
--sink_stall : in std_logic;
source_stall : in std_logic;
valid : in std_logic;
reset_design : out std_logic;
sink_ready_ctrl : out std_logic;
source_packet_error : out std_logic_vector (1 downto 0) := (others => '0');
source_valid_ctrl : out std_logic;
stall : out std_logic
);
-- Declarations
end auk_dspip_avalon_streaming_controller_hpfir;
-- hds interface_end
architecture struct of auk_dspip_avalon_streaming_controller_hpfir is
-- signal stall_int : std_logic;
-- signal stall_reg : std_logic;
-- attribute maxfan : integer;
-- attribute maxfan of stall_reg : signal is 500;
begin
reset_design <= not reset_n;
--should not stop sending data to source module when the sink module is stalled
--should only stop sending when the source module is stalled
--Disable the FIR core when backpressure
stall <= source_stall;
source_valid_ctrl <= valid;
-- Sink FIFO and FIR core are disabled at the same time
sink_ready_ctrl <= not(source_stall);
source_packet_error <= sink_packet_error;
end struct;
ld3/dds_vhdl/fir_sim/auk_dspip_avalon_streaming_sink_hpfir.vhd
+545
View File
@@ -0,0 +1,545 @@
-- (C) 2001-2019 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files from any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License Subscription
-- Agreement, Intel FPGA IP License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Intel and sold by
-- Intel or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------
-------------------------------------------------------------------------
--
-- Revision Control Information
--
-- $Revision: #1 $
-- $Date: 2009/07/29 $
-- Author : Boon Hong Oh
--
-- Project : Atlantic II Sink Interface with ready_latency=0
--
-- Description :
--
-- This interface is capable of handling single or multi channel streams as
-- well as blocks of data. The at_sink_sop and at_sink_eop must be fed as
-- described in the Atlantic II specification. The at_sink_error input is a 2-
-- bit signal that complies with the PFC error format (by Kent Orthner). The
-- error checking is extensively done, however the resulting information is
-- still mapped on the available 3 error states as shown below.
-- 00: no error
-- 01: missing sop
-- 10: missing eop
-- 11: unexpected eop
-- other types of errors also marked as 11.
--
-- ALTERA Confidential and Proprietary
-- Copyright 2006 (c) Altera Corporation
-- All rights reserved
--
-------------------------------------------------------------------------
-------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.auk_dspip_lib_pkg_hpfir.all;
use work.auk_dspip_math_pkg_hpfir.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity auk_dspip_avalon_streaming_sink_hpfir is
generic(
WIDTH_g : integer := 24; -- DATA_PORT_COUNT * DATA_WIDTH
DATA_WIDTH : integer := 8;
DATA_PORT_COUNT : integer := 3;
PACKET_SIZE_g : natural := 2
--FIFO_DEPTH_g : natural := 8 --if PFC mode is selected, this generic
--is used for passing the poly_factor.
--MIN_DATA_COUNT_g : natural := 2;
--PFC_MODE_g : boolean := false;
--SOP_EOP_CALC_g : boolean := false; -- calculate sop and eop rather than
-- reading value from fifo
--FAMILY_g : string := "Stratix II";
--MEM_TYPE_g : string := "Auto"
);
port(
clk : in std_logic;
reset_n : in std_logic;
----------------- DESIGN SIDE SIGNALS
data : out std_logic_vector(WIDTH_g-1 downto 0);
data_valid : out std_logic_vector(0 downto 0);
sink_ready_ctrl : in std_logic; --the controller will tell
--the interface whether
--new input can be accepted.
--sink_stall : out std_logic; --needs to stall the design
--if no new data is coming
packet_error : out std_logic_vector (1 downto 0); --this is for SOP and EOP check only.
--when any of these doesn't behave as
--expected, the error is flagged.
--send_sop : out std_logic; -- transmit SOP signal to the design.
-- It only transmits the legal SOP.
--send_eop : out std_logic; -- transmit EOP signal to the design.
-- It only transmits the legal EOP.
----------------- ATLANTIC SIDE SIGNALS
at_sink_ready : out std_logic; --it will be '1' whenever the
--sink_ready_ctrl signal is high.
at_sink_valid : in std_logic;
at_sink_data : in std_logic_vector(WIDTH_g-1 downto 0);
at_sink_sop : in std_logic := '0';
at_sink_eop : in std_logic := '0';
at_sink_error : in std_logic_vector(1 downto 0) := "00" --it indicates
--that there is an error in the packet.
);
end auk_dspip_avalon_streaming_sink_hpfir;
-- hds interface_end
architecture rtl of auk_dspip_avalon_streaming_sink_hpfir is
type STATE_TYPE_t is (start, stall, run1, st_err, end1); -- stall,run_once,wait1,
type OUT_STATE_TYPE_t is (normal, empty_and_not_ready, empty_and_ready);
constant LOG2PACKET_SIZE_c : natural := log2_ceil_one(PACKET_SIZE_g);
signal sink_state : STATE_TYPE_t;
signal sink_next_state : STATE_TYPE_t;
signal reset_count : std_logic;
signal count_enable : std_logic;
signal count : unsigned(LOG2PACKET_SIZE_c -1 downto 0);
signal count_finished : boolean;
signal at_sink_error_int : std_logic;
signal packet_error_int : std_logic_vector (1 downto 0);
signal packet_error_s : std_logic_vector(1 downto 0);
signal at_sink_ready_s : std_logic;
--signal reset : std_logic;
signal max_reached : boolean; -- flag to show counter has reached max value
-- component altera_avalon_sc_fifo is
-- generic(
-- SYMBOLS_PER_BEAT : integer := 1;
-- BITS_PER_SYMBOL : integer := 8;
-- FIFO_DEPTH : integer := 16;
-- CHANNEL_WIDTH : integer := 0;
-- ERROR_WIDTH : integer := 0;
-- USE_PACKETS : integer := 0
-- );
-- port (
-- -- inputs:
-- signal clk : IN STD_LOGIC;
-- signal in_data : IN STD_LOGIC_VECTOR (DATA_WIDTH*DATA_PORT_COUNT-1 DOWNTO 0);
-- signal in_valid : IN STD_LOGIC;
-- signal in_startofpacket : IN STD_LOGIC;
-- signal in_endofpacket : IN STD_LOGIC;
-- signal out_ready : IN STD_LOGIC;
-- signal reset : IN STD_LOGIC;
--
-- signal in_empty : IN STD_LOGIC_VECTOR (log2_ceil_one(DATA_PORT_COUNT)-1 DOWNTO 0);
-- signal in_error : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
-- signal in_channel : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
--
-- signal csr_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- signal csr_write : IN STD_LOGIC;
-- signal csr_read : IN STD_LOGIC;
-- signal csr_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
--
-- -- outputs:
-- signal in_ready : OUT STD_LOGIC;
-- signal out_data : OUT STD_LOGIC_VECTOR (DATA_WIDTH*DATA_PORT_COUNT-1 DOWNTO 0);
-- signal out_valid : OUT STD_LOGIC;
--
-- signal out_empty : OUT STD_LOGIC_VECTOR (log2_ceil_one(DATA_PORT_COUNT)-1 DOWNTO 0);
-- signal out_error : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
-- signal out_channel : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
-- );
-- end component altera_avalon_sc_fifo;
begin
valid_generate_single : if PACKET_SIZE_g = 1 generate
signal packet_error0 : std_logic;
begin
at_sink_error_int <= at_sink_error(0) when at_sink_valid = '1' else
'0';
packet_error_int <= '0' & packet_error0;
packet_error0 <= '0' when at_sink_error_int = '0' and sink_next_state /= st_err else
'1';
sink_comb_update_1 : process (sink_state, at_sink_valid, at_sink_error_int, at_sink_ready_s)
begin -- process sink_comb_update_1
case sink_state is
when start =>
--fifo_wrreq <= '0';
if at_sink_error_int = '1' then
sink_next_state <= st_err;
else
if at_sink_ready_s = '0' and at_sink_valid = '0' then
sink_next_state <= start;
elsif at_sink_ready_s = '0' and at_sink_valid = '1' then
sink_next_state <= start;
elsif at_sink_ready_s = '1' and at_sink_valid = '0' then
sink_next_state <= stall;
elsif at_sink_ready_s = '1' and at_sink_valid = '1' then
sink_next_state <= run1;
else
sink_next_state <= st_err;
end if;
end if;
when stall =>
--fifo_wrreq <= '0';
if at_sink_error_int = '1' then
sink_next_state <= st_err;
else
if at_sink_ready_s = '0' and at_sink_valid = '0' then
sink_next_state <= start;
elsif at_sink_ready_s = '0' and at_sink_valid = '1' then
sink_next_state <= start;
elsif at_sink_ready_s = '1' and at_sink_valid = '0' then
sink_next_state <= stall;
elsif at_sink_ready_s = '1' and at_sink_valid = '1' then
sink_next_state <= run1;
else
sink_next_state <= st_err;
end if;
end if;
when run1 =>
--fifo_wrreq <= '1';
if at_sink_error_int = '1' then
sink_next_state <= st_err;
else
if at_sink_ready_s = '0' and at_sink_valid = '0' then
sink_next_state <= start;
elsif at_sink_ready_s = '0' and at_sink_valid = '1' then
sink_next_state <= start;
elsif at_sink_ready_s = '1' and at_sink_valid = '0' then
sink_next_state <= stall;
elsif at_sink_ready_s = '1' and at_sink_valid = '1' then
sink_next_state <= run1;
else
sink_next_state <= st_err;
end if;
end if;
when st_err =>
--fifo_wrreq <= '0';
if at_sink_error_int = '1' then
sink_next_state <= st_err;
else
if at_sink_ready_s = '0' and at_sink_valid = '0' then
sink_next_state <= start;
elsif at_sink_ready_s = '0' and at_sink_valid = '1' then
sink_next_state <= start;
elsif at_sink_ready_s = '1' and at_sink_valid = '0' then
sink_next_state <= stall;
elsif at_sink_ready_s = '1' and at_sink_valid = '1' then
sink_next_state <= run1;
else
sink_next_state <= st_err;
end if;
end if;
when others =>
sink_next_state <= st_err;
--fifo_wrreq <= '0';
end case;
end process sink_comb_update_1;
end generate valid_generate_single;
valid_generate_mult : if PACKET_SIZE_g > 1 generate
at_sink_error_int <= at_sink_error(1) or at_sink_error(0) when at_sink_valid = '1' else
'0';
count_enable <= '1' when (sink_next_state = run1 or sink_next_state = end1) else --
--or sink_next_state = run_once) else
'0';
reset_count <= '1' when sink_next_state = st_err else
'0';
sink_comb_update_2 : process (sink_state, at_sink_ready_s, at_sink_valid,
at_sink_error, at_sink_error_int, at_sink_sop,
at_sink_eop, count, count_finished)
begin -- process sink_comb_update_2
case sink_state is
when start =>
--fifo_wrreq <= '0';
if at_sink_error_int = '1' then
sink_next_state <= st_err;
packet_error_int <= at_sink_error;
else
if at_sink_ready_s = '1' and at_sink_valid = '1' and at_sink_sop = '1' then
sink_next_state <= run1;
packet_error_int <= "00";
elsif (at_sink_ready_s = '1' and at_sink_valid = '1' and at_sink_sop = '0') then
sink_next_state <= st_err;
packet_error_int <= "01";
else
sink_next_state <= start;
packet_error_int <= "00";
end if;
end if;
when run1 =>
--fifo_wrreq <= '1';
if at_sink_error_int = '1' then
sink_next_state <= st_err;
packet_error_int <= at_sink_error;
elsif at_sink_sop = '1' and at_sink_valid = '1' then
sink_next_state <= st_err;
packet_error_int <= "01";
elsif (count_finished = false and at_sink_eop = '1' and at_sink_valid = '1') then
sink_next_state <= st_err;
packet_error_int <= "11";
else
if at_sink_eop = '0' and count_finished = false and at_sink_valid = '1' and at_sink_ready_s = '1' then
sink_next_state <= run1;
packet_error_int <= "00";
elsif at_sink_eop = '1' and count_finished = true and at_sink_valid = '1' and at_sink_ready_s = '1' then
sink_next_state <= end1;
packet_error_int <= "00";
elsif (count_finished = true and at_sink_valid = '0' and at_sink_ready_s = '1') or
(at_sink_valid = '0' and at_sink_ready_s = '1') then
sink_next_state <= stall;
packet_error_int <= "00";
elsif (count_finished = true and at_sink_ready_s = '0') or (at_sink_eop = '0' and at_sink_ready_s = '0') then
sink_next_state <= stall; --wait1;
packet_error_int <= "00";
elsif (count_finished = true and at_sink_eop = '0' and at_sink_valid = '1' and at_sink_ready_s = '1') then
sink_next_state <= st_err;
packet_error_int <= "10";
else
sink_next_state <= st_err;
packet_error_int <= "11";
end if;
end if;
when stall =>
--fifo_wrreq <= '0';
if at_sink_error_int = '1' then
sink_next_state <= st_err;
packet_error_int <= at_sink_error;
elsif at_sink_sop = '1' and at_sink_valid = '1' then
sink_next_state <= st_err;
packet_error_int <= "01";
elsif (count_finished = false and at_sink_eop = '1' and at_sink_valid = '1') then
sink_next_state <= st_err;
packet_error_int <= "11";
else
if at_sink_eop = '0' and count_finished = false and at_sink_valid = '1' and at_sink_ready_s = '1' then --and at_sink_ready_int = '1' then
sink_next_state <= run1;
packet_error_int <= "00";
elsif at_sink_eop = '1' and count_finished = true and at_sink_valid = '1' and at_sink_ready_s = '1' then
sink_next_state <= end1;
packet_error_int <= "00";
elsif (count_finished = true and at_sink_valid = '0') or -- and at_sink_ready_s = '1') or
(at_sink_valid = '0' and at_sink_ready_s = '1') then
sink_next_state <= stall;
packet_error_int <= "00";
elsif (count_finished = true and at_sink_ready_s = '0') or (at_sink_eop = '0' and at_sink_ready_s = '0') then
sink_next_state <= stall; --wait1;
packet_error_int <= "00";
elsif (count_finished = true and at_sink_eop = '0' and at_sink_valid = '1' and at_sink_ready_s = '1') then
sink_next_state <= st_err;
packet_error_int <= "10";
else
sink_next_state <= st_err;
packet_error_int <= "11";
end if;
end if;
when end1 =>
--fifo_wrreq <= '1';
if at_sink_error_int = '1' then
sink_next_state <= st_err;
packet_error_int <= at_sink_error;
else
if at_sink_ready_s = '1' and at_sink_valid = '1' and at_sink_sop = '1' then
sink_next_state <= run1;
packet_error_int <= "00";
elsif (at_sink_valid = '1' and at_sink_sop = '0') then
sink_next_state <= st_err;
packet_error_int <= "01";
else
sink_next_state <= start;
packet_error_int <= "00";
end if;
end if;
when st_err =>
--fifo_wrreq <= '0';
if at_sink_error_int = '1' then
sink_next_state <= st_err;
packet_error_int <= at_sink_error;
else
if at_sink_ready_s = '1' and at_sink_valid = '1' and at_sink_sop = '1' then
sink_next_state <= run1;
packet_error_int <= "00";
elsif (at_sink_ready_s = '1' and at_sink_valid = '1' and at_sink_sop = '0') then
sink_next_state <= st_err;
packet_error_int <= "01";
else
sink_next_state <= start;
packet_error_int <= "00";
end if;
end if;
when others => null;
end case;
end process sink_comb_update_2;
counter : process (clk, reset_n)
begin -- process counter
if reset_n = '0' then
count <= (others => '0');
max_reached <= false;
elsif clk'event and clk = '1' then -- rising clock edge
if reset_count = '1' then
count <= (others => '0');
else
if count_enable = '1' then
if count = PACKET_SIZE_g-2 then
max_reached <= true;
else
max_reached <= false;
end if;
if max_reached = false then
count <= count + 1;
else
count <= (others => '0');
end if;
end if;
end if;
end if;
end process counter;
count_finished <= max_reached;
end generate valid_generate_mult;
sink_input_update : process (clk, reset_n)
begin -- process
if reset_n = '0' then
sink_state <= start;
elsif clk'event and clk = '1' then
sink_state <= sink_next_state;
end if;
end process sink_input_update;
-- sink_output_update : process (clk, reset_n)
-- begin -- process
-- if reset_n = '0' then
-- sink_out_state <= normal;
-- elsif clk'event and clk = '1' then
-- sink_out_state <= sink_out_next_state;
-- end if;
-- end process sink_output_update;
error_register : process (clk, reset_n)
begin -- process
if reset_n = '0' then
packet_error_s <= "00";
elsif clk'event and clk = '1' then
packet_error_s <= packet_error_int;
end if;
end process;
packet_error <= packet_error_s;
-----------------------------------------------------------------------------
-- This was included because the vho simulations of fifo produce 'X' in
-- reset whcih means that for the FFT, alll outputs go to X when sop = X
-----------------------------------------------------------------------------
--gen_calc_sop: if SOP_EOP_CALC_g = true generate
--
-- -- generate sop and eop separate
-- out_cnt_p : process (clk, reset)
-- begin -- process out_cnt_p
-- if reset = '1' then
-- fifo_rdreq_d <= '0';
-- out_cnt <= 0;
-- elsif rising_edge(clk) then
-- fifo_rdreq_d <= fifo_rdreq;
-- if fifo_rdreq = '1' then
-- if out_cnt < PACKET_SIZE_g - 1 then
-- out_cnt <= out_cnt + 1;
-- else
-- out_cnt <= 0;
-- end if;
-- end if;
-- end if;
-- end process out_cnt_p;
--
-- send_sop_eop_p : process (clk, reset)
-- begin -- process send_sop_eop_p
-- if reset = '1' then
-- send_sop_s <= '0';
-- send_eop_s <= '0';
-- elsif rising_edge(clk) then
-- if fifo_rdreq = '1' and sink_ready_ctrl = '1' then
-- send_sop_s <= '0';
-- send_eop_s <= '0';
-- if out_cnt = 0 then
-- send_sop_s <= '1';
-- end if;
-- if out_cnt = PACKET_SIZE_g - 1 then
-- send_eop_s <= '1';
-- end if;
-- end if;
-- end if;
-- end process send_sop_eop_p;
--
-- end generate gen_calc_sop;
--reset <= not reset_n;
at_sink_ready <= at_sink_ready_s;
at_sink_ready_s <= sink_ready_ctrl;
data <= at_sink_data;
data_valid(0) <= at_sink_valid;
-- sink_scfifo : altera_avalon_sc_fifo
-- generic map (
-- SYMBOLS_PER_BEAT => DATA_PORT_COUNT,
-- BITS_PER_SYMBOL => DATA_WIDTH,
-- FIFO_DEPTH => FIFO_DEPTH_g,
-- CHANNEL_WIDTH => 0,
-- ERROR_WIDTH => 0,
-- USE_PACKETS => 0)
-- port map (
-- clk => clk,
-- reset => reset,
-- in_ready => at_sink_ready_s,
-- in_data => at_sink_data,
-- in_valid => at_sink_valid,
-- in_startofpacket => '0',
-- in_endofpacket => '0',
-- out_ready => sink_ready_ctrl,
-- out_data => data,
-- out_valid => data_valid(0),
-- in_empty => (others => '0'),
-- in_error => (others => '0'),
-- in_channel => (others => '0'),
-- csr_address => (others => '0'),
-- csr_write => '0',
-- csr_read => '0',
-- csr_writedata => (others => '0'),
-- out_empty => open,
-- out_error => open,
-- out_channel => open);
end rtl;
ld3/dds_vhdl/fir_sim/auk_dspip_avalon_streaming_source_hpfir.vhd
+467
View File
@@ -0,0 +1,467 @@
-- (C) 2001-2019 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files from any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License Subscription
-- Agreement, Intel FPGA IP License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Intel and sold by
-- Intel or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------
-------------------------------------------------------------------------
--
-- Revision Control Information
--
-- $Revision: #1 $
-- $Date: 2009/07/29 $
-- Author : Boon Hong Oh
--
-- Project : Avalon_streaming II Source Interface with ready_latency=0
--
-- Description :
--
-- This interface is capable of handling single or multi channel streams as
-- well as blocks of data. The at_source_sop and at_source_eop are generated as
-- described in the Avalon_streaming II specification. The at_source_error output is a 2-
-- bit signal that complies with the PFC error format (by Kent Orthner).
--
-- 00: no error
-- 01: missing sop
-- 10: missing eop
-- 11: unexpected eop
-- other types of errors also marked as 11. Any error signal is accompanied
-- by at_sink_eop flagged high.
--
-- When packet_size is greater than one, this interface expects the main design
-- to supply the count of data starting from 1 to the packet_size. When it
-- receives the valid flag together with the data_count=1, it starts pumping
-- out data by flagging the at_source_sop and at_source_valid both high.
--
-- When the data_count=packet_size, the at_source_eop is flagged high together
-- with at_source_valid. THERE IS NO ERROR CHECKING FOR THE data_count signal.
--
-- If the receiver is not ready to accept any data, the interface flags the source_
-- stall signal high to tell the design to stall. It is the designers
-- responsibility to use this signal properly. In some design, the stall signal
-- needs to stall all of the design so that no new data can be accepted (as in
-- FIR), in other cases (i.e. a FIFO built on a dual port RAM),the input can
-- still accept new data although it cannot send any output.
--
-- ALTERA Confidential and Proprietary
-- Copyright 2006 (c) Altera Corporation
-- All rights reserved
--
-------------------------------------------------------------------------
-------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
use work.auk_dspip_math_pkg_hpfir.all;
entity auk_dspip_avalon_streaming_source_hpfir is
generic(
WIDTH_g : integer := 8; -- DATA_PORT_COUNT * DATA_WIDTH
DATA_WIDTH : integer := 8;
DATA_PORT_COUNT : integer := 1;
PACKET_SIZE_g : natural := 2;
FIFO_DEPTH_g : natural := 0;
HAVE_COUNTER_g : boolean := false;
COUNTER_LIMIT_g : natural := 4;
--MULTI_CHANNEL_g : boolean := true;
USE_PACKETS : integer := 1;
--FAMILY_g : string := "Stratix II";
--MEM_TYPE_g : string := "Auto";
ENABLE_BACKPRESSURE_g : boolean := true
);
port(
clk : in std_logic;
reset_n : in std_logic;
----------------- DESIGN SIDE SIGNALS
data_in : in std_logic_vector (WIDTH_g-1 downto 0);
data_count : in std_logic_vector (log2_ceil_one(PACKET_SIZE_g)-1 downto 0) := (others => '0');
source_valid_ctrl : in std_logic;
source_stall : out std_logic;
packet_error : in std_logic_vector (1 downto 0);
----------------- AVALON_STREAMING SIDE SIGNALS
at_source_ready : in std_logic;
at_source_valid : out std_logic;
at_source_data : out std_logic_vector (WIDTH_g-1 downto 0);
at_source_channel : out std_logic_vector (log2_ceil_one(PACKET_SIZE_g)-1 downto 0);
at_source_error : out std_logic_vector (1 downto 0);
at_source_sop : out std_logic;
at_source_eop : out std_logic
);
-- Declarations
end auk_dspip_avalon_streaming_source_hpfir;
-- hds interface_end
architecture rtl of auk_dspip_avalon_streaming_source_hpfir is
--constant FIFO_HINT_c : string := "RAM_BLOCK_TYPE="& MEM_TYPE_g;
constant FIFO_DEPTH_c : natural := FIFO_DEPTH_g;
constant LOG2PACKET_SIZE_c : natural := log2_ceil_one(PACKET_SIZE_g);
constant MIN_DATA_COUNT_g : natural := 2;
type STATE_TYPE_t is (start, sop, run1, st_err, end1); --wait1, stall,
signal source_state : STATE_TYPE_t;
signal source_next_state : STATE_TYPE_t;
signal packet_error0 : std_logic;
signal at_source_error_int : std_logic_vector(1 downto 0);
signal at_source_sop_int : std_logic := '0';
signal at_source_eop_int : std_logic := '0';
signal count_finished : boolean := false;
signal count_started : boolean := false;
signal at_source_valid_s : std_logic;
signal data_valid : std_logic;
signal data_out : std_logic_vector(WIDTH_g-1 downto 0);
signal fifo_count : std_logic_vector(DATA_PORT_COUNT*log2_ceil(FIFO_DEPTH_g)-1 downto 0);
signal fifo_empty : std_logic_vector(DATA_PORT_COUNT-1 downto 0); -- multichan, multiinout
signal fifo_alm_empty : std_logic_vector(DATA_PORT_COUNT-1 downto 0);
signal fifo_alm_full : std_logic_vector(DATA_PORT_COUNT-1 downto 0);
signal fifo_full : std_logic_vector(DATA_PORT_COUNT-1 downto 0);
signal clear_fifo : std_logic;
signal fifo_rdreq : std_logic;
signal fifo_rdreq_d : std_logic;
signal fifo_wrreq : std_logic;
signal fifo_empty_d : std_logic;
signal reset_design_int : std_logic;
signal channel_out : std_logic_vector(log2_ceil_one(PACKET_SIZE_g)-1 downto 0) := (others => '0');
signal fifo_sop_in : std_logic := '0';
signal fifo_eop_in : std_logic := '0';
signal fifo_error_in : std_logic_vector(1 downto 0);
signal at_source_sop_s : std_logic := '0';
signal at_source_eop_s : std_logic := '0';
signal at_source_error_s : std_logic_vector(1 downto 0);
signal in_ready : std_logic;
component altera_avalon_sc_fifo is
generic(
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 2;
ERROR_WIDTH : integer := 2;
--EMPTY_LATENCY : integer := 0;
USE_PACKETS : integer := 0
);
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal in_channel : IN STD_LOGIC_VECTOR (log2_ceil_one(PACKET_SIZE_g)-1 DOWNTO 0);
signal in_data : IN STD_LOGIC_VECTOR (DATA_WIDTH*DATA_PORT_COUNT-1 DOWNTO 0);
signal in_error : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal in_endofpacket : IN STD_LOGIC;
signal in_startofpacket : IN STD_LOGIC;
signal in_valid : IN STD_LOGIC;
signal out_ready : IN STD_LOGIC;
signal reset : IN STD_LOGIC;
signal in_empty : IN STD_LOGIC_VECTOR (log2_ceil_one(DATA_PORT_COUNT)-1 DOWNTO 0);
signal csr_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal csr_write : IN STD_LOGIC;
signal csr_read : IN STD_LOGIC;
signal csr_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal in_ready : OUT STD_LOGIC;
signal out_channel : OUT STD_LOGIC_VECTOR (log2_ceil_one(PACKET_SIZE_g)-1 DOWNTO 0);
signal out_data : OUT STD_LOGIC_VECTOR (DATA_WIDTH*DATA_PORT_COUNT-1 DOWNTO 0);
signal out_error : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal out_endofpacket : OUT STD_LOGIC;
signal out_startofpacket : OUT STD_LOGIC;
signal out_valid : OUT STD_LOGIC;
signal out_empty : OUT STD_LOGIC_VECTOR (log2_ceil_one(DATA_PORT_COUNT)-1 DOWNTO 0)
);
end component altera_avalon_sc_fifo;
begin
single_channel : if USE_PACKETS = 0 generate
at_source_sop_int <= '0';
at_source_eop_int <= '0';
packet_error0 <= packet_error(0);
at_source_error_int(1) <= '0';
at_source_error_int(0) <= packet_error0;
end generate single_channel;
packet_multi : if USE_PACKETS = 1 generate
packet_error0 <= packet_error(1) or packet_error(0);
counter_no : if HAVE_COUNTER_g = false generate
signal data_counter : unsigned(LOG2PACKET_SIZE_c-1 downto 0);
begin
count_finished <= true when data_counter = to_unsigned(PACKET_SIZE_g-1, LOG2PACKET_SIZE_c) else
false;
data_counter <= unsigned(data_count);
count_started <= true when data_counter = 0 else
false;
end generate counter_no;
counter_yes : if HAVE_COUNTER_g = true generate
signal data_counter : unsigned(log2_ceil(COUNTER_LIMIT_g)-1 downto 0);
begin
count_finished <= true when data_counter = to_unsigned(COUNTER_LIMIT_g-1, log2_ceil(COUNTER_LIMIT_g)) else
false;
count_started <= true when data_counter = 0 else
false;
packet_counter : process (clk, reset_n)
begin -- process packet_counter
if reset_n = '0' then
data_counter <= (others => '0');
elsif rising_edge(clk) then
if source_state = start and source_next_state = sop then
data_counter <= --(others => '0'); --
data_counter +1;
elsif data_valid = '1' and at_source_ready = '1' and (data_counter < COUNTER_LIMIT_g-1) then
data_counter <= data_counter +1;
elsif count_finished = true then
data_counter <= (others => '0');
end if;
end if;
end process packet_counter;
end generate counter_yes;
source_comb_update : process (--at_source_ready,
count_finished, count_started,
packet_error, packet_error0, source_state,
--at_source_valid_s
in_ready,
source_valid_ctrl)
begin -- process source_comb_update
case source_state is
when start =>
if packet_error0 = '1' then
source_next_state <= st_err;
at_source_error_int <= packet_error;
at_source_sop_int <= '0';
at_source_eop_int <= '1';
else
at_source_eop_int <= '0';
at_source_error_int <= "00";
if source_valid_ctrl = '1' and count_started = true then --and at_source_ready='1' then
source_next_state <= sop;
at_source_sop_int <= '1';
else
source_next_state <= start;
at_source_sop_int <= '0';
end if;
end if;
when sop =>
if packet_error0 = '1' then
source_next_state <= st_err;
at_source_error_int <= packet_error;
at_source_sop_int <= '0';
at_source_eop_int <= '1';
else
at_source_error_int <= "00";
at_source_eop_int <= '0';
--if source_valid_ctrl = '1' and at_source_ready = '1' and count_finished = false then
if source_valid_ctrl = '1' and in_ready = '1' and count_finished = false then
if PACKET_SIZE_g > 2 then
source_next_state <= run1;
else
source_next_state <= end1;
end if;
at_source_sop_int <= '0';
--elsif (at_source_ready = '1' and source_valid_ctrl = '1' and count_finished = true) or
elsif (in_ready = '1' and source_valid_ctrl = '1' and count_finished = true) or
(source_valid_ctrl = '0' and count_finished = true) then --valid_ctrl_int = '1' and
source_next_state <= end1;
at_source_error_int <= "00";
at_source_eop_int <= '1';
at_source_sop_int <= '0';
else
source_next_state <= sop;
at_source_sop_int <= '1';
end if;
end if;
when run1 =>
at_source_sop_int <= '0';
if packet_error0 = '1' then
source_next_state <= st_err;
at_source_error_int <= packet_error;
at_source_eop_int <= '1';
else
--if (at_source_ready = '1' and source_valid_ctrl = '1' and count_finished = true) or
if (in_ready = '1' and source_valid_ctrl = '1' and count_finished = true) or
(source_valid_ctrl = '0' and count_finished = true) then --valid_ctrl_int = '1' and
source_next_state <= end1;
at_source_error_int <= "00";
at_source_eop_int <= '1';
else
source_next_state <= run1;
at_source_error_int <= "00";
at_source_eop_int <= '0';
end if;
end if;
when end1 =>
if packet_error0 = '1' then
source_next_state <= st_err;
at_source_error_int <= packet_error;
at_source_sop_int <= '0';
at_source_eop_int <= '1';
else
at_source_error_int <= "00";
--if source_valid_ctrl = '1' and count_started = true and at_source_ready = '1' then
if source_valid_ctrl = '1' and count_started = true and in_ready = '1' then
source_next_state <= sop;
at_source_sop_int <= '1';
at_source_eop_int <= '0';
--elsif source_valid_ctrl = '1' and at_source_ready = '1' then
elsif source_valid_ctrl = '1' and in_ready = '1' then
source_next_state <= start;
at_source_sop_int <= '0';
at_source_eop_int <= '0';
else
source_next_state <= end1;
at_source_sop_int <= '0';
at_source_eop_int <= '1';
end if;
end if;
when st_err =>
at_source_sop_int <= '0';
at_source_eop_int <= '0';
if packet_error0 = '1' then
source_next_state <= st_err;
at_source_error_int <= packet_error;
else
source_next_state <= start;
at_source_error_int <= "00";
end if;
when others =>
source_next_state <= st_err;
at_source_sop_int <= '0';
at_source_eop_int <= '1';
at_source_error_int <= "11";
end case;
end process source_comb_update;
source_state_update : process (clk, reset_n)
begin -- process
if reset_n = '0' then
source_state <= start;
elsif clk'event and clk = '1' then
source_state <= source_next_state;
end if;
end process source_state_update;
end generate packet_multi;
at_source_sop <= at_source_sop_s;
at_source_eop <= at_source_eop_s;
at_source_error <= at_source_error_s;
channel_info_exists : if USE_PACKETS = 1 generate
at_source_channel <= channel_out;
end generate channel_info_exists;
no_channel_info : if USE_PACKETS = 0 generate
at_source_channel <= (others => '0');
end generate no_channel_info;
at_source_data <= data_out;
at_source_valid <= data_valid;
backpressure_support: if ENABLE_BACKPRESSURE_g = true generate
reset_design_int <= not reset_n;
--source_stall <= not(in_ready);
source_stall <= not(at_source_ready);
fifo_sop_in <= '0' when USE_PACKETS = 0 else
at_source_sop_int;
fifo_eop_in <= '0' when USE_PACKETS = 0 else
at_source_eop_int;
fifo_error_in <= "00" when USE_PACKETS = 0 else
at_source_error_int;
scfifo : altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => DATA_PORT_COUNT,
BITS_PER_SYMBOL => DATA_WIDTH,
FIFO_DEPTH => FIFO_DEPTH_c,
CHANNEL_WIDTH => log2_ceil_one(PACKET_SIZE_g),
ERROR_WIDTH => 2,
--EMPTY_LATENCY => 1,
USE_PACKETS => USE_PACKETS)
port map (
clk => clk,
reset => reset_design_int,
in_ready => in_ready,
--in_data => fifo_datain(((0*DATA_WIDTH)+DATA_WIDTH-1) downto (0*DATA_WIDTH)),
in_data => data_in,
in_valid => source_valid_ctrl,
in_error => fifo_error_in,
in_channel => data_count,
in_startofpacket => fifo_sop_in,
in_endofpacket => fifo_eop_in,
in_empty => (others => '0'),
csr_address => (others => '0'),
csr_write => '0',
csr_read => '0',
csr_writedata => (others => '0'),
out_ready => at_source_ready,
--out_data => fifo_dataout(((0*DATA_WIDTH)+DATA_WIDTH-1) downto (0*DATA_WIDTH)),
out_data => data_out,
out_valid => data_valid,
out_error => at_source_error_s,
out_channel => channel_out,
out_startofpacket => at_source_sop_s,
out_endofpacket => at_source_eop_s,
out_empty => open);
end generate backpressure_support;
backpressure_no_support: if ENABLE_BACKPRESSURE_g = false generate
in_ready <= '1';
source_stall <= '0';
output_registers : process (clk, reset_n)
begin
if reset_n = '0' then
channel_out <= (others => '0');
data_out <= (others => '0');
data_valid <= '0';
at_source_error_s <= "00";
at_source_sop_s <= '0';
at_source_eop_s <= '0';
elsif rising_edge(clk) then
channel_out <= data_count;
data_out <= data_in;
data_valid <= source_valid_ctrl;
at_source_error_s <= at_source_error_int;
at_source_sop_s <= at_source_sop_int;
at_source_eop_s <= at_source_eop_int;
end if;
end process output_registers;
end generate backpressure_no_support;
end rtl;
ld3/dds_vhdl/fir_sim/auk_dspip_lib_pkg_hpfir.vhd
+583
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@@ -0,0 +1,583 @@
-- (C) 2001-2019 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files from any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License Subscription
-- Agreement, Intel FPGA IP License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Intel and sold by
-- Intel or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Alex, 02-10-07, this package declaration results in error at built time on a new machine
--
use work.auk_dspip_math_pkg_hpfir.all;
package auk_dspip_lib_pkg_hpfir is
--Component names:
--auk_dspip_atlantic_sink
--auk_dspip_atlantic_source
--auk_dspip_interface_controller
--auk_dspip_avalon_streaming_controller_hpfir
--auk_dspip_avalon_streaming_controller_pe_fir_91
--auk_dspip_avalon_streaming_sink_hpfir
--auk_dspip_avalon_streaming_source_hpfir
--auk_dspip_delay_fir_91
--auk_dspip_fastadd_fir_91
--auk_dspip_fastaddsub_fir_91
--auk_dspip_pipelined_adder_fir_91
--auk_dspip_fast_accumulator_fir_91
--auk_dspip_fifo_pfc_fir_91
--auk_dspip_fpcompiler_alufp
--auk_dspip_fpcompiler_aslf
--auk_dspip_fpcompiler_asrf
--auk_dspip_fpcompiler_castftox
--auk_dspip_fpcompiler_castxtof
--auk_dspip_fpcompiler_clzf
--auk_dspip_fpcompiler_mulfp
--auk_dspip_pfc_fir_91
--auk_dspip_roundsat_fir_91
component auk_dspip_atlantic_sink is
generic(
WIDTH : integer := 16;
PACKET_SIZE : natural := 4;
log2packet_size : integer := 2
);
port(
clk : in std_logic;
reset_n : in std_logic;
----------------- DESIGN SIDE SIGNALS
data_available : out std_logic; --goes high when new data is available
data : out std_logic_vector(WIDTH-1 downto 0);
sink_ready_ctrl : in std_logic; --the controller will tell
--the interface whether
--new input can be accepted.
sink_stall : out std_logic; --needs to stall the design
--if no new data is coming
packet_error : out std_logic_vector (1 downto 0); --this is for SOP and EOP check only.
--when any of these doesn't behave as
--expected, the error is flagged.
send_sop : out std_logic; -- transmit SOP signal to the design.
-- It only transmits the legal SOP.
send_eop : out std_logic; -- transmit EOP signal to the design.
-- It only transmits the legal EOP.
----------------- ATLANTIC SIDE SIGNALS
at_sink_ready : out std_logic; --it will be '1' whenever the
--sink_ready_ctrl signal is high.
at_sink_valid : in std_logic;
at_sink_data : in std_logic_vector(WIDTH-1 downto 0);
at_sink_sop : in std_logic := '0';
at_sink_eop : in std_logic := '0';
at_sink_error : in std_logic_vector(1 downto 0) --it indicates to the data source
--that the SOP and EOP signals
--are not received as expected.
);
end component auk_dspip_atlantic_sink;
component auk_dspip_atlantic_source is
generic(
WIDTH : integer := 16;
packet_size : natural := 4;
LOG2packet_size : integer := 2;
multi_channel : BOOLEAN := TRUE
);
port(
clk : in std_logic;
reset_n : in std_logic;
----------------- DESIGN SIDE SIGNALS
data : in std_logic_vector (WIDTH-1 downto 0);
data_count : in std_logic_vector (LOG2packet_size-1 downto 0) := (others => '0');
source_valid_ctrl : in std_logic; --the controller will tell
--the interface whether
--new input can be accepted.
source_stall : out std_logic; --needs to stall the design
--if no new data is coming
packet_error : in std_logic_vector (1 downto 0);
----------------- ATLANTIC SIDE SIGNALS
at_source_ready : in std_logic;
at_source_valid : out std_logic;
at_source_data : out std_logic_vector (WIDTH-1 downto 0);
at_source_channel : out std_logic_vector (log2packet_size-1 downto 0);
at_source_error : out std_logic_vector (1 downto 0);
at_source_sop : out std_logic;
at_source_eop : out std_logic
);
-- Declarations
end component auk_dspip_atlantic_source;
component auk_dspip_interface_controller IS
PORT(
clk : in std_logic;
reset : IN std_logic;
ready : in std_logic;
sink_packet_error : IN std_logic_vector (1 DOWNTO 0);
sink_stall : IN std_logic;
source_stall : IN std_logic;
valid : IN std_logic;
reset_design : OUT std_logic;
reset_n : OUT std_logic;
sink_ready_ctrl : OUT std_logic;
source_packet_error : OUT std_logic_vector (1 DOWNTO 0);
source_valid_ctrl : OUT std_logic;
stall : OUT std_logic
);
-- Declarations
end component auk_dspip_interface_controller ;
component auk_dspip_avalon_streaming_controller_hpfir is
port(
clk : in std_logic;
--clk_en : in std_logic := '1';
reset_n : in std_logic;
--ready : in std_logic;
sink_packet_error : in std_logic_vector (1 downto 0);
--sink_stall : in std_logic;
source_stall : in std_logic;
valid : in std_logic;
reset_design : out std_logic;
sink_ready_ctrl : out std_logic;
source_packet_error : out std_logic_vector (1 downto 0);
source_valid_ctrl : out std_logic;
stall : out std_logic
);
-- Declarations
end component auk_dspip_avalon_streaming_controller_hpfir;
component auk_dspip_avalon_streaming_controller_pe_fir_91 is
generic (
FIFO_WIDTH_g : natural := 8;
ENABLE_PIPELINE_DEPTH_g : natural := 0; -- this value should match the depth of the enable pipeline in the core
FAMILY_g : string := "Stratix II";
MEM_TYPE_g : string := "Auto"
);
port(
clk : in std_logic;
clk_en : in std_logic := '1';
reset_n : in std_logic;
ready : in std_logic;
sink_packet_error : in std_logic_vector (1 downto 0);
sink_stall : in std_logic;
source_stall : in std_logic;
valid : in std_logic;
reset_design : out std_logic;
sink_ready_ctrl : out std_logic;
source_packet_error : out std_logic_vector (1 downto 0);
source_valid_ctrl : out std_logic;
stall : out std_logic;
data_in : in std_logic_vector(FIFO_WIDTH_g-1 downto 0);
data_out : out std_logic_vector(FIFO_WIDTH_g-1 downto 0);
design_stall : out std_logic
);
-- Declarations
end component auk_dspip_avalon_streaming_controller_pe_fir_91;
component auk_dspip_avalon_streaming_sink_hpfir is
generic(
WIDTH_g : integer := 16;
DATA_WIDTH : integer := 8;
DATA_PORT_COUNT : integer := 3;
PACKET_SIZE_g : natural := 4
--FIFO_DEPTH_g : natural := 5 --if PFC mode is selected, this generic
--is used for passing the poly_factor.
--MIN_DATA_COUNT_g : natural := 2;
--PFC_MODE_g : boolean := false;
--SOP_EOP_CALC_g : boolean := false; -- calculate sop and eop rather than
-- reading value from fifo
--FAMILY_g : string := "Stratix II";
--MEM_TYPE_g : string := "Auto"
);
port(
clk : in std_logic;
reset_n : in std_logic;
----------------- DESIGN SIDE SIGNALS
data : out std_logic_vector(WIDTH_g-1 downto 0);
data_valid : out std_logic_vector(0 downto 0);
sink_ready_ctrl : in std_logic; --the controller will tell
--the interface whether
--new input can be accepted.
--sink_stall : out std_logic; --needs to stall the design
--if no new data is coming
packet_error : out std_logic_vector (1 downto 0); --this is for SOP and EOP check only.
--when any of these doesn't behave as
--expected, the error is flagged.
--send_sop : out std_logic; -- transmit SOP signal to the design.
-- It only transmits the legal SOP.
--send_eop : out std_logic; -- transmit EOP signal to the design.
-- It only transmits the legal EOP.
----------------- ATLANTIC SIDE SIGNALS
at_sink_ready : out std_logic; --it will be '1' whenever the
--sink_ready_ctrl signal is high.
at_sink_valid : in std_logic;
at_sink_data : in std_logic_vector(WIDTH_g-1 downto 0);
at_sink_sop : in std_logic := '0';
at_sink_eop : in std_logic := '0';
at_sink_error : in std_logic_vector(1 downto 0) := "00" --it indicates
--that there is an error in the packet.
);
end component auk_dspip_avalon_streaming_sink_hpfir;
component auk_dspip_avalon_streaming_source_hpfir is
generic(
WIDTH_g : integer := 8;
DATA_WIDTH : integer := 8;
DATA_PORT_COUNT : integer := 1;
PACKET_SIZE_g : natural := 2;
FIFO_DEPTH_g : natural := 0;
HAVE_COUNTER_g : boolean := false;
COUNTER_LIMIT_g : natural := 4;
--MULTI_CHANNEL_g : boolean := true;
USE_PACKETS : integer := 1;
--FAMILY_g : string := "Stratix II";
--MEM_TYPE_g : string := "Auto";
ENABLE_BACKPRESSURE_g : boolean := true
);
port(
clk : in std_logic;
reset_n : in std_logic;
----------------- DESIGN SIDE SIGNALS
data_in : in std_logic_vector (WIDTH_g-1 downto 0);
data_count : in std_logic_vector (log2_ceil_one(PACKET_SIZE_g)-1 downto 0) := (others => '0');
source_valid_ctrl : in std_logic;
source_stall : out std_logic;
packet_error : in std_logic_vector (1 downto 0);
----------------- AVALON_STREAMING SIDE SIGNALS
at_source_ready : in std_logic;
at_source_valid : out std_logic;
at_source_data : out std_logic_vector (WIDTH_g-1 downto 0);
at_source_channel : out std_logic_vector (log2_ceil_one(PACKET_SIZE_g)-1 downto 0);
at_source_error : out std_logic_vector (1 downto 0);
at_source_sop : out std_logic;
at_source_eop : out std_logic
);
-- Declarations
end component auk_dspip_avalon_streaming_source_hpfir;
component auk_dspip_roundsat_hpfir is
generic (
IN_WIDTH_g : natural := 8; -- i/p data width
REM_LSB_BIT_g : natural := 2; -- no. of lsb to be removed
REM_LSB_TYPE_g : string := "trunc"; -- trunc/round
REM_MSB_BIT_g : natural := 2; -- no. of msb to be removed
REM_MSB_TYPE_g : string := "trunc" -- trunc/sat
);
port (
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(IN_WIDTH_g-1 downto 0);
valid : out std_logic;
dataout : out std_logic_vector(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0)
);
end component auk_dspip_roundsat_hpfir;
component auk_dspip_delay_fir_91 is
generic (
WIDTH_g : natural := 8; -- data width
DELAY_g : natural := 8;
-- number of clock cycles the input
-- will be delayed by
MEMORY_TYPE_g : string := "AUTO";
-- possible values are "m4k", "m512",
-- "register", "mram", "auto",
-- "lutram", "M9K", "M144K".
-- Any other string will be interpreted
-- as "auto"
REGISTER_FIRST_g : natural := 1;
-- if "1", the first delay is guaranteed
-- to be in registers
REGISTER_LAST_g : natural := 1); -- if "1", the last delay is guaranteed
-- to be in registers
port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic; -- global clock enable
datain : in std_logic_vector(WIDTH_g-1 downto 0);
dataout : out std_logic_vector(WIDTH_g-1 downto 0)
);
end component auk_dspip_delay_fir_91;
component auk_dspip_fastadd_fir_91 is
generic (
INWIDTH_g : natural := 18;
LABWIDTH_g : natural := 16);
-- width of lab in selected device ( 10 or 16 in Cyclone,
-- Cylone II, Stratix and Stratix II. Don't know
-- Stratix III yet.
port (
datain1 : in std_logic_vector(INWIDTH_g-1 downto 0);
datain2 : in std_logic_vector(INWIDTH_g-1 downto 0);
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
dataout : out std_logic_vector(INWIDTH_g downto 0));
end component auk_dspip_fastadd_fir_91;
component auk_dspip_fastaddsub_fir_91 is
generic (
INWIDTH_g : natural := 18;
LABWIDTH_g : natural := 16);
-- width of lab in selected device ( 10 or 16 in Cyclone,
-- Cylone II, Stratix and Stratix II. Don't know
-- Stratix III yet.
port (
datain1 : in std_logic_vector(INWIDTH_g-1 downto 0);
datain2 : in std_logic_vector(INWIDTH_g-1 downto 0);
add_nsub : in std_logic;
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
dataout : out std_logic_vector(INWIDTH_g downto 0));
end component auk_dspip_fastaddsub_fir_91;
component auk_dspip_pipelined_adder_fir_91 is
generic (
INWIDTH_g : natural := 42;
-- width of lab in selected device ( 10 or 16 in Cyclone,
-- Cylone II, Stratix and Stratix II.
-- Alex : should I use 19 bits for Stratix III?
-- The rational being 10 ALM (2 bits x ALM + the carry chain inside the same LAB for efficiency.
LABWIDTH_g : natural := 38);
port (
datain1 : in std_logic_vector(INWIDTH_g-1 downto 0);
datain2 : in std_logic_vector(INWIDTH_g-1 downto 0);
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
dataout : out std_logic_vector(INWIDTH_g downto 0));
end component auk_dspip_pipelined_adder_fir_91;
component auk_dspip_fast_accumulator_fir_91 is
generic (
DATA_WIDTH_g : natural := 42;
-- width of lab in selected device ( 10 or 16 in Cyclone,
-- Cylone II, Stratix and Stratix II.
-- for Stratix III is 20 so labwidth should be set to 18.
-- The rational being 10 ALM (2 bits x ALM + the carry chain inside the same LAB for efficiency.
LABWIDTH_g : natural := 38;
NUM_OF_CHANNELS_g : natural := 1;
ACCUM_OUT_WIDTH_g : natural := 48;
ACCUM_MEM_TYPE_g : string := "auto");
port (
reset : in std_logic;
clk : in std_logic;
enb : in std_logic;
add_to_zero : in std_logic;
datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0);
datao : out std_logic_vector(ACCUM_OUT_WIDTH_g-1 downto 0));
end component auk_dspip_fast_accumulator_fir_91;
component auk_dspip_fifo_pfc_fir_91 is
generic (
NUM_CHANNELS_g : integer := 5;
POLY_FACTOR_g : integer := 3;
DATA_WIDTH_g : integer := 16;
ALMOST_FULL_VALUE_g : integer := 2;
RAM_TYPE_g : string := "AUTO";
CALCULATE_USED_WORDS_ONCE : boolean := true
);
port (
datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0);
datao : out std_logic_vector(DATA_WIDTH_g-1 downto 0);
channel_out : out std_logic_vector(log2_ceil(NUM_CHANNELS_g)-1 downto 0);
used_w : out std_logic_vector(log2_ceil(POLY_FACTOR_g * NUM_CHANNELS_g)+1 downto 0);
wrreq : in std_logic;
rdreq : in std_logic;
almost_full : out std_logic;
empty : out std_logic;
sclr : in std_logic;
clk : in std_logic;
reset : in std_logic;
enable : in std_logic
);
end component auk_dspip_fifo_pfc_fir_91;
component auk_dspip_fpcompiler_alufp is
port (
sysclk : in std_logic;
reset : in std_logic;
enable : in std_logic;
addsub : in std_logic;
aa : in std_logic_vector (42 downto 1);
aasat, aazip : in std_logic;
bb : in std_logic_vector (42 downto 1);
bbsat, bbzip : in std_logic;
cc : out std_logic_vector (42 downto 1);
ccsat, cczip : out std_logic
);
end component auk_dspip_fpcompiler_alufp;
component auk_dspip_fpcompiler_aslf is
port (
inbus : in std_logic_vector (32 downto 1);
shift : in std_logic_vector (5 downto 1);
outbus : out std_logic_vector (32 downto 1)
);
end component auk_dspip_fpcompiler_aslf;
component auk_dspip_fpcompiler_asrf is
port (
inbus : in std_logic_vector (32 downto 1);
shift : in std_logic_vector (5 downto 1);
outbus : out std_logic_vector (32 downto 1)
);
end component auk_dspip_fpcompiler_asrf;
component auk_dspip_fpcompiler_castftox is
port (
aa : in std_logic_vector (32 downto 1);
cc : out std_logic_vector (42 downto 1);
ccsat, cczip : out std_logic
);
end component auk_dspip_fpcompiler_castftox;
component auk_dspip_fpcompiler_castxtof is
port (
sysclk : in std_logic;
reset : in std_logic;
enable : in std_logic;
aa : in std_logic_vector (42 downto 1);
aasat, aazip : in std_logic;
cc : out std_logic_vector (32 downto 1)
);
end component auk_dspip_fpcompiler_castxtof;
component auk_dspip_fpcompiler_clzf is
port (
frac : in std_logic_vector (32 downto 1);
count : out std_logic_vector (5 downto 1)
);
end component auk_dspip_fpcompiler_clzf;
component auk_dspip_fpcompiler_mulfp is
port (
sysclk : in std_logic;
reset : in std_logic;
enable : in std_logic;
aa : in std_logic_vector (42 downto 1);
aasat, aazip : in std_logic;
bb : in std_logic_vector (42 downto 1);
bbsat, bbzip : in std_logic;
cc : out std_logic_vector (42 downto 1);
ccsat, cczip : out std_logic
);
end component auk_dspip_fpcompiler_mulfp;
component auk_dspip_pfc_fir_91 is
generic (
NUM_CHANNELS_g : integer := 5;
POLY_FACTOR_g : integer := 3;
DATA_WIDTH_g : integer := 16;
RAM_TYPE_g : string := "AUTO"
);
port (
datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0);
datao : out std_logic_vector(DATA_WIDTH_g-1 downto 0);
channel_out : out std_logic_vector(log2_ceil(NUM_CHANNELS_g)-1 downto 0);
in_valid : in std_logic;
out_valid : out std_logic;
clk : in std_logic;
reset : in std_logic;
enable : in std_logic
);
end component auk_dspip_pfc_fir_91;
component auk_dspip_roundsat_fir_91 is
generic (
IN_WIDTH_g : natural := 8; -- data width
OUT_WIDTH_g : natural := 8; -- data width
ROUNDING_TYPE_g : string := "TRUNCATE_LOW"
);
port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic; -- global clock enable
datain : in std_logic_vector(IN_WIDTH_g-1 downto 0);
dataout : out std_logic_vector(OUT_WIDTH_g-1 downto 0));
end component auk_dspip_roundsat_fir_91;
component auk_dspip_avalon_streaming_block_source_fir_91 is
generic (
MAX_BLK_g : natural;
DATAWIDTH_g : natural);
port (
clk : in std_logic;
reset : in std_logic;
in_blk : in std_logic_vector(log2_ceil(MAX_BLK_g) downto 0);
in_valid : in std_logic;
source_stall : out std_logic;
in_data : in std_logic_vector(DATAWIDTH_g - 1 downto 0);
source_valid : out std_logic;
source_ready : in std_logic;
source_sop : out std_logic;
source_eop : out std_logic;
source_data : out std_logic_vector(DATAWIDTH_g - 1 downto 0));
end component auk_dspip_avalon_streaming_block_source_fir_91;
component auk_dspip_avalon_streaming_block_sink_fir_91 is
generic (
MAX_BLK_g : natural;
STALL_g : natural;
DATAWIDTH_g : natural;
-- this generic is specific for the FFT.
NUM_STAGES_g : natural);
port (
clk : in std_logic;
reset : in std_logic;
in_blk : in std_logic_vector(log2_ceil(MAX_BLK_g) downto 0);
in_sop : in std_logic;
in_eop : in std_logic;
in_inverse : in std_logic;
sink_valid : in std_logic;
sink_ready : out std_logic;
source_stall : in std_logic;
in_data : in std_logic_vector(DATAWIDTH_g - 1 downto 0);
processing : in std_logic;
in_error : in std_logic_vector(1 downto 0);
out_error : out std_logic_vector(1 downto 0);
out_valid : out std_logic;
out_sop : out std_logic;
out_eop : out std_logic;
out_data : out std_logic_vector(DATAWIDTH_g - 1 downto 0);
curr_blk : out std_logic_vector(log2_ceil(MAX_BLK_g) downto 0);
-- these are specific to the FFT, no effort has been made to optimize!
curr_pwr_2 : out std_logic;
curr_inverse : out std_logic;
curr_input_sel : out std_logic_vector(NUM_STAGES_g - 1 downto 0));
end component auk_dspip_avalon_streaming_block_sink_fir_91;
end package auk_dspip_lib_pkg_hpfir;
ld3/dds_vhdl/fir_sim/auk_dspip_math_pkg_hpfir.vhd
+370
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@@ -0,0 +1,370 @@
-- (C) 2001-2019 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files from any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License Subscription
-- Agreement, Intel FPGA IP License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Intel and sold by
-- Intel or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-- (C) 2001-2009 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------
-------------------------------------------------------------------------
--
-- Revision Control Information
--
-- $Revision: #1 $
-- $Date: 2009/07/29 $
-- Check in by : $Author: max $
-- Author : DSP_IP
--
-- Project : <project name>
--
-- Description :
--
-- Common functions for DSP_IP cores.
--
--
-- ALTERA Confidential and Proprietary
-- Copyright 2006 (c) Altera Corporation
-- All rights reserved
--
-------------------------------------------------------------------------
-------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
PACKAGE auk_dspip_math_pkg_hpfir IS
-----------------------------------------------------------------------------
-- NOTE that these log functions are not intended to synthesize directly
-- into hardware, rather they are used to generate constants for
-- synthesized hardware.
-----------------------------------------------------------------------------
---------------------------------------------------------------------------
-- LOG2_CEIL Function.
-- Effectively performs log2() followed by ceil()
-- e.g. CEIL_LOG2(255) returns 8
-- CEIL_LOG2(256) returns 8
-- CEIL_LOG2(257) returns 9
---------------------------------------------------------------------------
function log2_ceil(arg : in integer) return integer;
function log2_ceil_one(arg : in integer) return integer; -- log2_ceil(1)=0
---------------------------------------------------------------------------
-- LOG2_FLOOR Function.
-- Effectively performs log2() followed by floor()
-- e.g. CEIL_LOG2(255) returns 7
-- CEIL_LOG2(256) returns 8
-- CEIL_LOG2(257) returns 8
---------------------------------------------------------------------------
function log2_floor(arg : in integer) return integer;
-----------------------------------------------------------------------------
-- SIGN functions
-----------------------------------------------------------------------------
-- returns the sign bit of a vector
function sign (arg : in signed) return std_logic;
-- sign extends ARG to size SIZE.
function sign_extend (arg : signed; size : positive) return signed;
-- sign extend one bit
function xt1 (arg : signed) return signed;
---------------------------------------------------------------------------
-- Arithmetic FUNCTIONs.
---------------------------------------------------------------------------
-- Check integer for odd-ness
function is_odd(arg : integer) return boolean;
-----------------------------------------------------------------------------
-- Logical functions
-----------------------------------------------------------------------------
-- Result of and'ing all of the bits of the vector.
function and_reduce(arg : std_logic_vector) return std_logic;
function and_reduce(arg : unsigned) return std_logic;
-- Result of or'ing all of the bits of the vector.
function or_reduce(arg : std_logic_vector) return std_logic;
function or_reduce(arg : unsigned) return std_logic;
-- returns index+1 of the highest asserted bit.
function highest_one(arg : unsigned) return natural;
-- returns index+1 of the lowest asserted bit.
function lowest_one(arg : unsigned) return natural;
-- returns the count of number of ones.
function count_ones(arg : unsigned) return natural;
-- Bit reverse
function bit_reverse(arg : unsigned) return unsigned;
-- Invert the argument bitwise
function invert(arg : unsigned) return unsigned;
--Halve towards up
function halve_ceil(arg:natural) return natural;
function div_ceil(a:natural;b:natural) return natural;
END PACKAGE auk_dspip_math_pkg_hpfir;
package body auk_dspip_math_pkg_hpfir is
---------------------------------------------------------------------------
-- LOG2_CEIL Function.
---------------------------------------------------------------------------
function log2_ceil(arg : in integer) return integer is
variable res : integer;
begin
res := 0;
for i in 0 to 30 loop
if (arg > (2**i)) then
res := i+1;
end if;
end loop; -- i
return res;
end log2_ceil;
---------------------------------------------------------------------------
-- LOG2_CEIL_ONE Function.
---------------------------------------------------------------------------
function log2_ceil_one(arg : in integer) return integer is
variable res : integer;
begin
res := 0;
for i in 0 to 30 loop
if (arg > (2**i)) then
res := i+1;
end if;
end loop; -- i
if res = 0 then
res := 1;
end if;
return res;
end log2_ceil_one;
---------------------------------------------------------------------------
-- LOG2_FLOOR Function.
-----------------------------------------------------------------------------
function log2_floor(arg : in integer) return integer is
variable res : integer;
begin
res := 0;
for i in 0 to 30 loop
if (arg >= (2**i)) then
res := i;
end if;
end loop; -- i
return res;
end log2_floor;
-----------------------------------------------------------------------------
-- SIGN Function
-----------------------------------------------------------------------------
function sign (arg : in signed) return std_logic is
variable res : std_logic;
begin
res := arg(arg'left);
return(res);
end sign;
-----------------------------------------------------------------------------
-- SIGN_EXTEND Function
-----------------------------------------------------------------------------
function sign_extend (arg : signed; size : positive) return signed is
variable res : signed(size-1 downto 0);
begin
if arg'length > size then
assert arg'length < size report "WARNING, can't sign extend" severity warning;
end if;
for i in arg'length to size-1 loop
res(i) := arg(arg'left);
end loop; -- i
res(arg'length-1 downto 0) := arg;
return(res);
end sign_extend;
-----------------------------------------------------------------------------
-- XT1 Function
-----------------------------------------------------------------------------
function xt1 (arg : signed) return signed is
variable res : signed(arg'length downto 0);
begin
res := arg(arg'left) & arg;
return(res);
end xt1;
-----------------------------------------------------------------------------
-- IS_ODD Function
-----------------------------------------------------------------------------
function is_odd(arg : integer) return boolean is
begin
return ((arg mod 2) = 1);
end is_odd;
-----------------------------------------------------------------------------
-- AND_REDUCE Function
-----------------------------------------------------------------------------
function and_reduce(arg : std_logic_vector) return std_logic is
variable res : std_logic;
begin
res := '1';
for i in arg'range loop
res := res and arg(i);
end loop;
return res;
end;
function and_reduce(arg : unsigned) return std_logic is
variable res : std_logic;
begin
res := '1';
for i in arg'range loop
res := res and arg(i);
end loop;
return res;
end;
-----------------------------------------------------------------------------
-- OR_REDUCE Function
-----------------------------------------------------------------------------
function or_reduce(arg : unsigned) return std_logic is
variable res : std_logic;
begin
res := '0';
for i in arg'range loop
res := res or arg(i);
end loop;
return res;
end;
function or_reduce(arg : std_logic_vector) return std_logic is
variable res : std_logic;
begin
res := '0';
for i in arg'range loop
res := res or arg(i);
end loop;
return res;
end;
---------------------------------------------------------------------------
-- HIGHEST_ONE Function.
---------------------------------------------------------------------------
-- Returns index+1 of the highest asserted bit, or 0 if no bit set.
-- Vector is evaluated from left to right, not high to low!
function highest_one(arg : unsigned) return natural is
begin
for i in arg'range loop
if arg(i) = '1' then
return i+1;
end if;
end loop;
return 0;
end;
-----------------------------------------------------------------------------
-- LOWEST_ONE Function
-----------------------------------------------------------------------------
-- Returns index+1 of the lowest asserted bit, or 0 if no bit set.
-- Vector is evaluated from left to right, not high to low!
function lowest_one(arg : unsigned) return natural is
begin
for i in 0 to arg'length-1 loop
if (arg(i) = '1') then
return(i+1);
end if;
end loop;
return(0);
end;
-----------------------------------------------------------------------------
-- COUNT_ONES
---------------------------------------------------------------------------
-- Returns the count of the number of ones.
function count_ones(arg : unsigned) return natural is
variable count : integer;
begin
count := 0;
for i in 0 to arg'length-1 loop
if (arg(i) = '1') then
count := count + 1;
end if;
end loop;
return count;
end;
-----------------------------------------------------------------------------
-- BIT_REVERSE function
-----------------------------------------------------------------------------
function bit_reverse(arg : unsigned) return unsigned is
variable res : unsigned(arg'range);
begin
for i in arg'range loop
res(i) := arg(arg'high - i);
end loop;
return(res);
end;
-----------------------------------------------------------------------------
-- INVERT Function
-----------------------------------------------------------------------------
function invert(arg : unsigned)
return unsigned -- (word'high downto 0)
is
variable res : unsigned(arg'high downto 0);
begin
for i in arg'range loop
res(i) := not arg(i);
end loop;
return (res);
end invert;
-----------------------------------------------------------------------------
-- HALVE_CEIL Function
-----------------------------------------------------------------------------
function halve_ceil(arg : natural) return natural is
variable res : natural;
begin
if is_odd(arg) then
res := (arg+1)/2;
else
res := arg/2;
end if;
return (res);
end halve_ceil;
-------------------------------------------------------------------------------
-- DIV_CEIL function
-------------------------------------------------------------------------------
function div_ceil(a : natural; b : natural) return natural is
variable res : natural := a/b;
begin
if res*b /= a then
res := res +1;
end if;
return res;
end div_ceil;
end package body auk_dspip_math_pkg_hpfir;
ld3/dds_vhdl/fir_sim/auk_dspip_roundsat_hpfir.vhd
+187
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-- (C) 2001-2019 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files from any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License Subscription
-- Agreement, Intel FPGA IP License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Intel and sold by
-- Intel or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------
-------------------------------------------------------------------------
--
-- Revision Control Information
--
-- $RCSfile: auk_dspip_roundsat_hpfir.vhd,v $
--
-- $Revision: #1 $
-- $Date: 2010/08/19 $
-- Check in by : $Author: max $
--
-- Description :
-- Implement output options for HP-FIR
--
-- ALTERA Confidential and Proprietary
-- Copyright 2006 (c) Altera Corporation
-- All rights reserved
--
-------------------------------------------------------------------------
-------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity auk_dspip_roundsat_hpfir is
generic (
IN_WIDTH_g : natural := 8; -- i/p data width
REM_LSB_BIT_g : natural := 2; -- no. of lsb to be removed
REM_LSB_TYPE_g : string := "trunc"; -- trunc/round
REM_MSB_BIT_g : natural := 2; -- no. of msb to be removed
REM_MSB_TYPE_g : string := "trunc" -- trunc/sat
);
port (
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(IN_WIDTH_g-1 downto 0);
valid : out std_logic;
dataout : out std_logic_vector(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0)
);
end entity auk_dspip_roundsat_hpfir;
architecture beh of auk_dspip_roundsat_hpfir is
signal data_lsb : std_logic_vector(IN_WIDTH_g-REM_LSB_BIT_g-1 downto 0);
signal valid_lsb : std_logic;
signal data_msb : std_logic_vector(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0);
constant zero_vec : std_logic_vector := std_logic_vector(to_signed(0, REM_LSB_BIT_g));
begin -- architecture beh
-----------------------------------------------------------------------------
-- lsb : trunc/round-up (symmetric)
-----------------------------------------------------------------------------
remove_lsb: if REM_LSB_BIT_g > 0 generate
begin
trunc_lsb: if REM_LSB_TYPE_g = "trunc" generate
begin
data_lsb <= datain(IN_WIDTH_g-1 downto REM_LSB_BIT_g);
valid_lsb <= enable;
end generate trunc_lsb;
rndup_lsb: if REM_LSB_TYPE_g = "round" generate
round_up_sym_p : process (clk, reset_n)
variable OR_accu : std_logic := '0';
begin
if reset_n = '0' then
data_lsb <= (others => '0');
valid_lsb <= '0';
elsif rising_edge(clk) then
if enable = '1' then
OR_accu := '0';
for i in 0 to REM_LSB_BIT_g-2 loop
OR_accu := OR_accu or datain(i);
end loop;
-- negative value
if (datain(IN_WIDTH_g-1) = '1') then
-- larger than -x.5 : rounded to -x
if (datain(REM_LSB_BIT_g-1)='1' and OR_accu='1') then
data_lsb <= std_logic_vector(signed(datain(IN_WIDTH_g-1 downto REM_LSB_BIT_g))+1);
-- less than or equal -x.5 : rounded to -x + 1
else
data_lsb <= datain(IN_WIDTH_g-1 downto REM_LSB_BIT_g);
end if;
-- positive value
else
-- maximum positive value
if datain(IN_WIDTH_g-1 downto REM_LSB_BIT_g-1) = std_logic_vector(to_signed(2**(IN_WIDTH_g-REM_LSB_BIT_g)-1, IN_WIDTH_g-REM_LSB_BIT_g+1)) then
data_lsb <= std_logic_vector(to_signed( 2**(IN_WIDTH_g-REM_LSB_BIT_g-1)-1, IN_WIDTH_g-REM_LSB_BIT_g));
-- larger than or equal x.5 : rounded to x + 1
elsif datain(REM_LSB_BIT_g-1) = '1' then
data_lsb <= std_logic_vector(signed(datain(IN_WIDTH_g-1 downto REM_LSB_BIT_g))+1);
-- less than x.5 : rounded to x
else
data_lsb <= datain(IN_WIDTH_g-1 downto REM_LSB_BIT_g);
end if;
end if;
end if;
valid_lsb <= enable;
end if;
end process round_up_sym_p;
end generate rndup_lsb;
end generate remove_lsb;
-----------------------------------------------------------------------------
-- keep lsb
-----------------------------------------------------------------------------
keep_lsb: if REM_LSB_BIT_g = 0 generate
begin
data_lsb <= datain;
valid_lsb <= enable;
end generate keep_lsb;
-----------------------------------------------------------------------------
-- msb : trunc/saturation
-----------------------------------------------------------------------------
remove_msb: if REM_MSB_BIT_g > 0 generate
signal min_val, max_val : std_logic_vector(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0);
begin
trunc_msb: if REM_MSB_TYPE_g = "trunc" generate
begin
data_msb <= data_lsb(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0);
dataout <= data_msb;
valid <= valid_lsb;
end generate trunc_msb;
sat_msb: if REM_MSB_TYPE_g = "sat" generate
max_val(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1) <= '0';
max_val(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-2 downto 0) <= (others => '1');
min_val(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1) <= '1';
min_val(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-2 downto 0) <= (others => '0');
data_msb <= std_logic_vector(max_val) when signed(data_lsb) > signed(max_val) else
std_logic_vector(min_val) when signed(data_lsb) < signed(min_val) else
data_lsb(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0);
msb_p : process (clk, reset_n)
begin
if reset_n = '0' then
dataout <= (others => '0');
valid <= '0';
elsif rising_edge(clk) then
if valid_lsb = '1' then
dataout <= data_msb;
end if;
valid <= valid_lsb;
end if;
end process msb_p;
end generate sat_msb;
end generate remove_msb;
-----------------------------------------------------------------------------
-- keep msb
-----------------------------------------------------------------------------
keep_msb: if REM_MSB_BIT_g = 0 generate
begin
data_msb <= data_lsb;
dataout <= data_msb;
valid <= valid_lsb;
end generate keep_msb;
-----------------------------------------------------------------------------
-- error checking:
-- Have we got a valid round mode?
-- Is the input greater than the output?
-----------------------------------------------------------------------------
assert (REM_LSB_TYPE_g = "trunc" or
REM_LSB_TYPE_g = "round" or
REM_MSB_TYPE_g = "trunc" or
REM_MSB_TYPE_g = "sat"
) report "Please check your round type and its spelling. Currently, we only support trunc, and round for LSB, trunc and sat for MSB" severity error;
end architecture beh;
ld3/dds_vhdl/fir_sim/cadence/cds.lib
+24
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@@ -0,0 +1,24 @@
DEFINE std $CDS_ROOT/tools/inca/files/STD/
DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/
DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/
DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/
DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/
DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/
DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/
DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/
DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
DEFINE work ./libraries/work/
DEFINE altera_ver ./libraries/altera_ver/
DEFINE lpm_ver ./libraries/lpm_ver/
DEFINE sgate_ver ./libraries/sgate_ver/
DEFINE altera_mf_ver ./libraries/altera_mf_ver/
DEFINE cyclonev_ver ./libraries/cyclonev_ver/
DEFINE cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver/
DEFINE cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver/
DEFINE altera ./libraries/altera/
DEFINE lpm ./libraries/lpm/
DEFINE sgate ./libraries/sgate/
DEFINE altera_mf ./libraries/altera_mf/
DEFINE altera_lnsim ./libraries/altera_lnsim/
DEFINE cyclonev ./libraries/cyclonev/
ld3/dds_vhdl/fir_sim/cadence/hdl.var
+2
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@@ -0,0 +1,2 @@
DEFINE WORK work
ld3/dds_vhdl/fir_sim/cadence/ncsim_setup.sh
+227
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@@ -0,0 +1,227 @@
# (C) 2001-2020 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Altera
# Program License Subscription Agreement, Altera MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 19.1 670 win32 2020.06.09.18:16:15
# ----------------------------------------
# ncsim - auto-generated simulation script
# ----------------------------------------
# This script provides commands to simulate the following IP detected in
# your Quartus project:
# fir
#
# Altera recommends that you source this Quartus-generated IP simulation
# script from your own customized top-level script, and avoid editing this
# generated script.
#
# To write a top-level shell script that compiles Altera simulation libraries
# and the Quartus-generated IP in your project, along with your design and
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
# into a new file, e.g. named "ncsim.sh", and modify text as directed.
#
# You can also modify the simulation flow to suit your needs. Set the
# following variables to 1 to disable their corresponding processes:
# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
# - SKIP_COM: skip compiling Quartus-generated IP simulation files
# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
#
# ----------------------------------------
# # TOP-LEVEL TEMPLATE - BEGIN
# #
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
# # construct paths to the files required to simulate the IP in your Quartus
# # project. By default, the IP script assumes that you are launching the
# # simulator from the IP script location. If launching from another
# # location, set QSYS_SIMDIR to the output directory you specified when you
# # generated the IP script, relative to the directory from which you launch
# # the simulator. In this case, you must also copy the generated files
# # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated -
# # into the location from which you launch the simulator, or incorporate
# # into any existing library setup.
# #
# # Run Quartus-generated IP simulation script once to compile Quartus EDA
# # simulation libraries and Quartus-generated IP simulation files, and copy
# # any ROM/RAM initialization files to the simulation directory.
# # - If necessary, specify any compilation options:
# # USER_DEFINED_COMPILE_OPTIONS
# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
# #
# source <script generation output directory>/cadence/ncsim_setup.sh \
# SKIP_ELAB=1 \
# SKIP_SIM=1 \
# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
# QSYS_SIMDIR=<script generation output directory>
# #
# # Compile all design files and testbench files, including the top level.
# # (These are all the files required for simulation other than the files
# # compiled by the IP script)
# #
# ncvlog <compilation options> <design and testbench files>
# #
# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
# # testbench module/entity name.
# #
# # Run the IP script again to elaborate and simulate the top level:
# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
# #
# source <script generation output directory>/cadence/ncsim_setup.sh \
# SKIP_FILE_COPY=1 \
# SKIP_DEV_COM=1 \
# SKIP_COM=1 \
# TOP_LEVEL_NAME=<simulation top> \
# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
# #
# # TOP-LEVEL TEMPLATE - END
# ----------------------------------------
#
# IP SIMULATION SCRIPT
# ----------------------------------------
# If fir is one of several IP cores in your
# Quartus project, you can generate a simulation script
# suitable for inclusion in your top-level simulation
# script by running the following command line:
#
# ip-setup-simulation --quartus-project=<quartus project>
#
# ip-setup-simulation will discover the Altera IP
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# ACDS 19.1 670 win32 2020.06.09.18:16:15
# ----------------------------------------
# initialize variables
TOP_LEVEL_NAME="fir"
QSYS_SIMDIR="./../"
QUARTUS_INSTALL_DIR="C:/intelfpga_lite/19.1/quartus/"
SKIP_FILE_COPY=0
SKIP_DEV_COM=0
SKIP_COM=0
SKIP_ELAB=0
SKIP_SIM=0
USER_DEFINED_ELAB_OPTIONS=""
USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
# ----------------------------------------
# overwrite variables - DO NOT MODIFY!
# This block evaluates each command line argument, typically used for
# overwriting variables. An example usage:
# sh <simulator>_setup.sh SKIP_SIM=1
for expression in "$@"; do
eval $expression
if [ $? -ne 0 ]; then
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
exit $?
fi
done
# ----------------------------------------
# initialize simulation properties - DO NOT MODIFY!
ELAB_OPTIONS=""
SIM_OPTIONS=""
if [[ `ncsim -version` != *"ncsim(64)"* ]]; then
:
else
:
fi
# ----------------------------------------
# create compilation libraries
mkdir -p ./libraries/work/
mkdir -p ./libraries/altera_ver/
mkdir -p ./libraries/lpm_ver/
mkdir -p ./libraries/sgate_ver/
mkdir -p ./libraries/altera_mf_ver/
mkdir -p ./libraries/cyclonev_ver/
mkdir -p ./libraries/cyclonev_hssi_ver/
mkdir -p ./libraries/cyclonev_pcie_hip_ver/
mkdir -p ./libraries/altera/
mkdir -p ./libraries/lpm/
mkdir -p ./libraries/sgate/
mkdir -p ./libraries/altera_mf/
mkdir -p ./libraries/altera_lnsim/
mkdir -p ./libraries/cyclonev/
# ----------------------------------------
# copy RAM/ROM files to simulation directory
# ----------------------------------------
# compile device library files
if [ $SKIP_DEV_COM -eq 0 ]; then
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf
ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_atoms_ncrypt.v" -work cyclonev
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd" -work cyclonev
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd" -work cyclonev
fi
# ----------------------------------------
# compile design files in correct order
if [ $SKIP_COM -eq 0 ]; then
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/dspba_library_package.vhd"
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/dspba_library.vhd"
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_math_pkg_hpfir.vhd"
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_lib_pkg_hpfir.vhd"
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_avalon_streaming_controller_hpfir.vhd"
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_avalon_streaming_sink_hpfir.vhd"
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_avalon_streaming_source_hpfir.vhd"
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_roundsat_hpfir.vhd"
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_avalon_sc_fifo.v"
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/fir_rtl_core.vhd"
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/fir_ast.vhd"
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/fir.vhd"
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/fir_tb.vhd"
fi
# ----------------------------------------
# elaborate top level design
if [ $SKIP_ELAB -eq 0 ]; then
export GENERIC_PARAM_COMPAT_CHECK=1
ncelab -access +w+r+c -namemap_mixgen -relax $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
fi
# ----------------------------------------
# simulate
if [ $SKIP_SIM -eq 0 ]; then
eval ncsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
fi
ld3/dds_vhdl/fir_sim/dspba_library.vhd
+377
View File
@@ -0,0 +1,377 @@
-- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Intel FPGA Software License Agreement,
-- Intel MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Intel and sold by
-- Intel or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_block: if 0 < depth generate
begin
delay_loop: for i in depth-1 downto 0 generate
begin
async_reset: if reset_kind = "ASYNC" generate
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind = "SYNC" generate
process(clk)
begin
if clk'event and clk='1' then
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
no_reset: if reset_kind = "NONE" generate
process(clk)
begin
if clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
end generate;
end generate;
xout <= delay_signals(0);
end delay;
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_sync_reg is
generic (
width1 : natural := 8;
init_value : std_logic_vector;
width2 : natural := 8;
depth : natural := 2;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end entity;
architecture sync_reg of dspba_sync_reg is
type bit_array is array (depth-1 downto 0) of std_logic;
signal iclk_enable : std_logic;
signal iclk_data : std_logic_vector(width1-1 downto 0);
signal oclk_data : std_logic_vector(width2-1 downto 0);
-- For Synthesis this means: preserve this registers and do not merge any other flip-flops with synchronizer flip-flops
-- For TimeQuest this means: identify these flip-flops as synchronizer to enable automatic MTBF analysis
signal sync_regs : bit_array;
attribute altera_attribute : string;
attribute altera_attribute of sync_regs : signal is "-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON";
signal oclk_enable : std_logic;
constant init_value_internal : std_logic_vector(width1-1 downto 0) := init_value;
signal counter : UNSIGNED(counter_width-1 downto 0);
signal ena_internal : std_logic;
begin
oclk_enable <= sync_regs(depth-1);
no_multiplication: if pulse_multiplier=1 generate
ena_internal <= ena(0);
end generate;
async_reset: if reset_kind="ASYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if aclr1=reset1_high then
counter <= (others => '0');
elsif clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1, aclr1)
begin
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
elsif clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2, aclr2)
begin
if aclr2=reset2_high then
sync_regs(i) <= '0';
elsif clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2, aclr2)
begin
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind="SYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
counter <= (others => '0');
else
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
else
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
sync_regs(i) <= '0';
else
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
none_reset: if reset_kind="NONE" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
xout <= iclk_data;
sxout <= oclk_data;
end sync_reg;
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dspba_pipe is
generic(
num_bits : positive := 8;
num_stages : natural := 0;
init_value : std_logic := 'X'
);
port(
clk: in std_logic;
d : in std_logic_vector(num_bits-1 downto 0);
q : out std_logic_vector(num_bits-1 downto 0)
);
end entity dspba_pipe;
architecture rtl of dspba_pipe is
attribute altera_attribute : string;
attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION off";
type stage_array_type is array(0 to num_stages) of std_logic_vector(num_bits-1 downto 0);
signal stage_array : stage_array_type := (others => (others => init_value));
begin
stage_array(0) <= d;
g_pipe : for i in 1 to num_stages generate
p_stage : process (clk) is
begin
if rising_edge(clk) then
stage_array(i) <= stage_array(i-1);
end if;
end process p_stage;
end generate g_pipe;
q <= stage_array(num_stages);
end rtl;
ld3/dds_vhdl/fir_sim/dspba_library_package.vhd
+72
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@@ -0,0 +1,72 @@
-- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Intel FPGA Software License Agreement,
-- Intel MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Intel and sold by
-- Intel or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_sync_reg is
generic (
width1 : natural := 8;
width2 : natural := 8;
depth : natural := 2;
init_value : std_logic_vector;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end component;
component dspba_pipe is
generic(
num_bits : positive;
num_stages : natural;
init_value : std_logic := 'X'
);
port(
clk: in std_logic;
d : in std_logic_vector(num_bits-1 downto 0);
q : out std_logic_vector(num_bits-1 downto 0)
);
end component dspba_pipe;
end dspba_library_package;
ld3/dds_vhdl/fir_sim/fir.vhd
+82
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@@ -0,0 +1,82 @@
-- (C) 2001-2019 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files from any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License Subscription
-- Agreement, Intel FPGA IP License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Intel and sold by
-- Intel or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.auk_dspip_lib_pkg_hpfir.all;
use work.auk_dspip_math_pkg_hpfir.all;
entity fir is
port (
clk : in STD_LOGIC;
reset_n : in STD_LOGIC;
ast_sink_data : in STD_LOGIC_VECTOR((0 + 1*16) * 1 + 0 - 1 downto 0);
ast_sink_valid : in STD_LOGIC;
ast_sink_error : in STD_LOGIC_VECTOR(1 downto 0);
ast_source_data : out STD_LOGIC_VECTOR(37 * 1*1 - 1 downto 0);
ast_source_valid : out STD_LOGIC;
ast_source_error : out STD_LOGIC_VECTOR(1 downto 0)
);
end fir;
architecture syn of fir is
component fir_ast
port (
clk : in STD_LOGIC;
reset_n : in STD_LOGIC;
ast_sink_data : in STD_LOGIC_VECTOR((0 + 1*16) * 1 + 0 - 1 downto 0);
ast_sink_valid : in STD_LOGIC;
ast_sink_ready : out STD_LOGIC;
ast_sink_sop : in STD_LOGIC;
ast_sink_eop : in STD_LOGIC;
ast_sink_error : in STD_LOGIC_VECTOR(1 downto 0);
ast_source_data : out STD_LOGIC_VECTOR(1*37 * 1 - 1 downto 0);
ast_source_ready : in STD_LOGIC;
ast_source_valid : out STD_LOGIC;
ast_source_sop : out STD_LOGIC;
ast_source_eop : out STD_LOGIC;
ast_source_channel : out STD_LOGIC_VECTOR(log2_ceil_one(1) - 1 downto 0);
ast_source_error : out STD_LOGIC_VECTOR(1 downto 0)
);
end component;
signal coeff_in_read_sig : std_logic;
begin
coeff_in_read_sig <= '1';
fir_ast_inst : fir_ast
port map (
clk => clk,
reset_n => reset_n,
ast_sink_data => ast_sink_data,
ast_source_data => ast_source_data,
ast_sink_valid => ast_sink_valid,
ast_sink_ready => open,
ast_source_ready => '1',
ast_source_valid => ast_source_valid,
ast_sink_sop => '0',
ast_sink_eop => '0',
ast_sink_error => ast_sink_error,
ast_source_sop => open,
ast_source_eop => open,
ast_source_channel => open,
ast_source_error => ast_source_error
);
end syn;
ld3/dds_vhdl/fir_sim/fir_ast.vhd
+273
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@@ -0,0 +1,273 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.auk_dspip_lib_pkg_hpfir.all;
use work.auk_dspip_math_pkg_hpfir.all;
entity fir_ast is
generic (
INWIDTH : integer := 16;
OUT_WIDTH_UNTRIMMED : integer := 37;
BANKINWIDTH : integer := 0;
REM_LSB_BIT_g : integer := 0;
REM_LSB_TYPE_g : string := "trunc";
REM_MSB_BIT_g : integer := 0;
REM_MSB_TYPE_g : string := "trunc";
PHYSCHANIN : integer := 1;
PHYSCHANOUT : integer := 1;
CHANSPERPHYIN : natural := 1;
CHANSPERPHYOUT : natural := 1;
OUTPUTFIFODEPTH : integer := 8;
USE_PACKETS : integer := 0;
MODE_WIDTH : integer := 0;
ENABLE_BACKPRESSURE : boolean := false;
LOG2_CHANSPERPHYOUT : natural := log2_ceil_one(1);
NUMCHANS : integer := 1;
DEVICE_FAMILY : string := "Cyclone V";
COMPLEX_CONST : integer := 1
);
port(
clk : in std_logic;
reset_n : in std_logic;
ast_sink_ready : out std_logic;
ast_source_data : out std_logic_vector(COMPLEX_CONST*(OUT_WIDTH_UNTRIMMED - REM_LSB_BIT_g - REM_MSB_BIT_g) * PHYSCHANOUT - 1 downto 0);
ast_sink_data : in std_logic_vector( COMPLEX_CONST*(INWIDTH + BANKINWIDTH) * PHYSCHANIN + MODE_WIDTH - 1 downto 0);
ast_sink_valid : in std_logic;
ast_source_valid : out std_logic;
ast_source_ready : in std_logic;
ast_source_eop : out std_logic;
ast_source_sop : out std_logic;
ast_source_channel : out std_logic_vector (LOG2_CHANSPERPHYOUT - 1 downto 0);
ast_sink_eop : in std_logic;
ast_sink_sop : in std_logic;
ast_sink_error : in std_logic_vector (1 downto 0);
ast_source_error : out std_logic_vector (1 downto 0)
);
attribute altera_attribute : string;
attribute altera_attribute of fir_ast:entity is "-name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 10036";
end fir_ast;
-- Warnings Suppression On
-- altera message_off 10036
architecture struct of fir_ast is
constant OUTWIDTH : integer := OUT_WIDTH_UNTRIMMED - REM_LSB_BIT_g - REM_MSB_BIT_g;
signal channel_out : std_logic_vector(LOG2_CHANSPERPHYOUT - 1 downto 0);
signal core_channel_out : std_logic_vector(2 -1 downto 0);
signal at_source_channel : std_logic_vector(2 -1 downto 0);
signal sink_packet_error : std_logic_vector(1 downto 0);
signal data_in : std_logic_vector((COMPLEX_CONST*INWIDTH + BANKINWIDTH) * PHYSCHANIN + MODE_WIDTH - 1 downto 0);
signal data_valid : std_logic_vector(0 downto 0);
signal data_out : std_logic_vector(COMPLEX_CONST*OUTWIDTH * PHYSCHANOUT -1 downto 0);
signal reset_fir : std_logic;
signal sink_ready_ctrl : std_logic;
signal source_packet_error : std_logic_vector(1 downto 0);
signal source_stall : std_logic;
signal source_valid_ctrl : std_logic;
signal stall : std_logic;
signal valid : std_logic;
signal core_valid : std_logic;
signal enable_in : std_logic_vector(0 downto 0);
signal outp_out : std_logic_vector(COMPLEX_CONST*OUTWIDTH * PHYSCHANOUT - 1 downto 0);
signal outp_blk_valid : std_logic_vector(PHYSCHANOUT - 1 downto 0);
signal core_out : std_logic_vector(OUT_WIDTH_UNTRIMMED * PHYSCHANOUT - 1 downto 0);
signal core_out_valid : std_logic_vector(0 downto 0);
signal core_out_channel : std_logic_vector(7 downto 0);
signal core_out_channel_0 : std_logic_vector(7 downto 0);
begin
sink : auk_dspip_avalon_streaming_sink_hpfir
generic map (
WIDTH_g => (COMPLEX_CONST*INWIDTH + BANKINWIDTH) * PHYSCHANIN + MODE_WIDTH,
DATA_WIDTH => (COMPLEX_CONST*INWIDTH + BANKINWIDTH) * PHYSCHANIN + MODE_WIDTH,
DATA_PORT_COUNT => 1,
PACKET_SIZE_g => CHANSPERPHYIN)
port map (
clk => clk,
reset_n => reset_n,
data => data_in,
data_valid => data_valid,
sink_ready_ctrl => sink_ready_ctrl,
packet_error => sink_packet_error,
at_sink_ready => ast_sink_ready,
at_sink_valid => ast_sink_valid,
at_sink_data => ast_sink_data,
at_sink_sop => ast_sink_sop,
at_sink_eop => ast_sink_eop,
at_sink_error => ast_sink_error);
source : auk_dspip_avalon_streaming_source_hpfir
generic map (
WIDTH_g => COMPLEX_CONST*OUTWIDTH * PHYSCHANOUT,
DATA_WIDTH => COMPLEX_CONST*OUTWIDTH,
DATA_PORT_COUNT => PHYSCHANOUT,
FIFO_DEPTH_g => OUTPUTFIFODEPTH,
USE_PACKETS => USE_PACKETS,
HAVE_COUNTER_g => false,
PACKET_SIZE_g => CHANSPERPHYOUT,
COUNTER_LIMIT_g => CHANSPERPHYOUT,
ENABLE_BACKPRESSURE_g => ENABLE_BACKPRESSURE)
port map (
clk => clk,
reset_n => reset_n,
data_in => data_out,
data_count => channel_out,
source_valid_ctrl => source_valid_ctrl,
source_stall => source_stall,
packet_error => source_packet_error,
at_source_ready => ast_source_ready,
at_source_valid => ast_source_valid,
at_source_data => ast_source_data,
at_source_channel => ast_source_channel,
at_source_sop => ast_source_sop,
at_source_eop => ast_source_eop,
at_source_error => ast_source_error);
intf_ctrl : auk_dspip_avalon_streaming_controller_hpfir
port map (
clk => clk,
reset_n => reset_n,
sink_packet_error => sink_packet_error,
source_stall => source_stall,
valid => valid,
reset_design => reset_fir,
sink_ready_ctrl => sink_ready_ctrl,
source_packet_error => source_packet_error,
source_valid_ctrl => source_valid_ctrl,
stall => stall);
multi_data_out: for m in PHYSCHANOUT-1 downto 0 generate
data_out(((m*OUTWIDTH)+OUTWIDTH-1) downto (m*OUTWIDTH)) <= outp_out(((m*OUTWIDTH)+OUTWIDTH-1) downto (m*OUTWIDTH));
end generate multi_data_out;
channel_pipe_lsb: if REM_LSB_TYPE_g = "round" and REM_LSB_BIT_g > 0 generate
begin
out_lsb_p : process (clk, reset_n)
begin
if reset_n = '0' then
core_out_channel_0 <= (others => '0');
elsif rising_edge(clk) then
core_out_channel_0 <= core_out_channel;
end if;
end process out_lsb_p;
end generate channel_pipe_lsb;
channel_wire_lsb: if REM_LSB_TYPE_g = "trunc" or REM_LSB_BIT_g = 0 generate
begin
core_out_channel_0 <= core_out_channel;
end generate channel_wire_lsb;
channel_pipe_msb: if REM_MSB_TYPE_g = "sat" and REM_MSB_BIT_g > 0 generate
begin
out_p : process (clk, reset_n)
begin
if reset_n = '0' then
channel_out <= (others => '0');
elsif rising_edge(clk) then
channel_out <= core_out_channel_0(LOG2_CHANSPERPHYOUT-1 downto 0);
end if;
end process out_p;
end generate channel_pipe_msb;
channel_wire_msb: if REM_MSB_TYPE_g = "trunc" or REM_MSB_BIT_g = 0 generate
begin
channel_out <= core_out_channel_0(LOG2_CHANSPERPHYOUT-1 downto 0);
end generate channel_wire_msb;
real_passthrough : if COMPLEX_CONST = 1 generate
component fir_rtl_core is
port (
xIn_v : in std_logic_vector(0 downto 0);
xIn_c : in std_logic_vector(7 downto 0);
xIn_0 : in std_logic_vector(16 - 1 downto 0);
xOut_v : out std_logic_vector(0 downto 0);
xOut_c : out std_logic_vector(7 downto 0);
xOut_0 : out std_logic_vector(37- 1 downto 0);
clk : in std_logic;
areset : in std_logic
);
end component fir_rtl_core;
--Complex data re-ordering
signal core_channel_out_core : std_logic_vector(2 -1 downto 0);
signal data_in_core : std_logic_vector((COMPLEX_CONST*INWIDTH + BANKINWIDTH) * PHYSCHANIN + MODE_WIDTH - 1 downto 0);
signal data_valid_core : std_logic_vector(0 downto 0);
signal core_out_core : std_logic_vector(OUT_WIDTH_UNTRIMMED * PHYSCHANOUT - 1 downto 0);
signal core_out_valid_core : std_logic_vector(0 downto 0);
signal core_out_channel_core : std_logic_vector(7 downto 0);
begin
hpfircore_core: fir_rtl_core
port map (
xIn_v => data_valid_core,
xIn_c => "00000000",
xIn_0 => data_in_core((0 + 16) * 0 + 16 - 1 downto (0 + 16) * 0),
xOut_v => core_out_valid_core,
xOut_c => core_out_channel_core,
xOut_0 => core_out_core(37* 0 + 37- 1 downto 37* 0),
clk => clk,
areset => reset_fir
);
core_channel_out <= core_channel_out_core;
data_in_core <= data_in;
data_valid_core <= data_valid;
core_out <= core_out_core;
core_out_valid(0) <= core_out_valid_core(0);
core_out_channel <= core_out_channel_core;
gen_outp_blk : for i in PHYSCHANOUT-1 downto 0 generate
begin
outp_blk : auk_dspip_roundsat_hpfir
generic map (
IN_WIDTH_g => OUT_WIDTH_UNTRIMMED ,
REM_LSB_BIT_g => REM_LSB_BIT_g ,
REM_LSB_TYPE_g => REM_LSB_TYPE_g ,
REM_MSB_BIT_g => REM_MSB_BIT_g ,
REM_MSB_TYPE_g => REM_MSB_TYPE_g
)
port map (
clk => clk,
reset_n => reset_n,
enable => core_out_valid(0),
datain => core_out(((i*OUT_WIDTH_UNTRIMMED)+OUT_WIDTH_UNTRIMMED-1) downto (i*OUT_WIDTH_UNTRIMMED)),
valid => outp_blk_valid(i),
dataout => outp_out(((i*OUTWIDTH)+OUTWIDTH-1) downto (i*OUTWIDTH))
);
end generate gen_outp_blk;
end generate real_passthrough;
valid <= outp_blk_valid(0);
enable_in(0) <= not stall;
end struct;
ld3/dds_vhdl/fir_sim/fir_coef_int.txt
+41
View File
@@ -0,0 +1,41 @@
-1299
-1264
-1050
-427
712
2350
4113
5360
5377
3686
267
-4309
-8868
-12055
-12679
-10168
-4790
2297
9348
14495
16382
14495
9348
2297
-4790
-10168
-12679
-12055
-8868
-4309
267
3686
5377
5360
4113
2350
712
-427
-1050
-1264
-1299
ld3/dds_vhdl/fir_sim/fir_input.txt
+165
View File
@@ -0,0 +1,165 @@
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-6804
-7424
-9673
11030
-17117
13591
-31248
14940
-21868
-17002
-15878
-7873
-18900
-9386
-14628
32567
4720
-19739
-13837
12911
16220
-18003
-2374
3596
24737
-4863
-24276
20032
31499
14450
98
9422
25309
-10432
-29523
-30326
-28282
-18678
-10718
14639
26177
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ld3/dds_vhdl/fir_sim/fir_mlab.m
+165
View File
@@ -0,0 +1,165 @@
%
%THIS IS A WIZARD GENERATED FILE. DO NOT EDIT THIS FILE!
%
%---------------------------------------------------------------------------------------------------------
%This is a filter with fixed coefficients.
%This Model Only Support Single Channel Input Data.
%Please input:
%data vector: stimulation(1:n)
% This Model Only Support FIR_WIDTH to 51 Bits
%FILTER PARAMETER
%Input Data Width: 16
%Interpolation Factor: 1
%Decimation Factor: 1
%FIR Width (Full Calculation Width Before Output Width Adjust) :37
%-----------------------------------------------------------------------------------------------------------
%MegaWizard Scaled Coefficient Values
function output = fir_mlab(stimulation, bank);
coef_matrix_in= [-1299,-1264,-1050,-427,712,2350,4113,5360,5377,3686,267,-4309,-8868,-12055,-12679,-10168,-4790,2297,9348,14495,16382,14495,9348,2297,-4790,-10168,-12679,-12055,-8868,-4309,267,3686,5377,5360,4113,2350,712,-427,-1050,-1264,-1299];
INTER_FACTOR = 1;
DECI_FACTOR = 1;
MSB_RM = 0;
MSB_TYPE = 0;
LSB_RM = 0;
LSB_TYPE = 0;
FIR_WIDTH = 37 + MSB_RM + LSB_RM;
OUT_WIDTH = 37 ; %37
DATA_WIDTH = 16;
% check size of inputs.
DY = size(stimulation, 2);
CY = size(coef_matrix_in, 2);
if CY ~= DY * INTER_FACTOR
fprintf('WARNING : coef_matrix size and input data size does not match\n');
end
%fill coef_matrix to length of data with the latest coef set
if CY < DY * INTER_FACTOR
coef_matrix = coef_matrix_in(bank + 1, :);
end
% check if input is integer
int_sti=round(stimulation);
T = (int_sti ~= stimulation);
if (max(T)~=0)
fprintf('WARNING : Integer Input Expected: Rounding Fractional Input to Nearest Integer...\n');
end
%Input overflow check
%set max/min for signed
maxdat = 2^(DATA_WIDTH-1)-1;
mindat = -maxdat-1;
%Saturating Input Value
a=find(int_sti>maxdat);
b=find(int_sti<mindat);
if (~isempty(a)|~isempty(b))
fprintf('WARNING : Input Amplitude Exceeds MAXIMUM/MINIMUM allowable values - saturating input values...\n');
lena = length (a);
lenb = length (b);
for i =1:lena
fprintf('%d > %d \n', int_sti(a(i)), maxdat);
int_sti(a(i)) = maxdat;
end
for i =1:lenb
fprintf('%d < %d \n', int_sti(b(i)), mindat);
int_sti(b(i)) = mindat;
end
end
% Add interpolation
inter_sti = zeros(1, INTER_FACTOR * length(int_sti));
inter_sti(1:INTER_FACTOR:INTER_FACTOR * length(int_sti)) = int_sti;
for i = 1 : DY *INTER_FACTOR
coef_current = coef_matrix(i,:);
output_temp(i) = simp_adaptive (inter_sti, coef_current, i);
end
% Truncate output
len1 = length(output_temp);
switch LSB_TYPE
case 0
%truncate
out_dec = bi_trunc_lsb(output_temp,LSB_RM,FIR_WIDTH);
case 1
%round
out_dec = bi_round(output_temp,LSB_RM, FIR_WIDTH);
end
switch MSB_TYPE
case 0
%truncate
out_dec = bi_trunc_msb(out_dec,MSB_RM,FIR_WIDTH-LSB_RM);
case 1
%round
out_dec = bi_satu(out_dec,MSB_RM, FIR_WIDTH-LSB_RM);
end
% choose decimation output in phase=DECI_FACTOR-1
if(DECI_FACTOR == 1)
output = out_dec;
else
output = out_dec(1:DECI_FACTOR:len1);
end
function[output, outindex] = simp_adaptive (int_sti, coef_current, data_index)
%Simulation is the whole input sequence
%coef_current is the current coefficient set
%data_index gives the last data to use
% output is the sum of input and coef multiplication
%outindex is the next data_index
coef_length = length(coef_current);
data_length = length(int_sti);
if (data_index > data_length)
fprintf('ERROR: DATA INDEX IS LARGER THAN DATA LENGTH!!!\n');
return
end
min_index = max(data_index - data_length, 1);
max_index = min(data_index, coef_length);
outindex= data_index+1;
output = int_sti(data_index + 1 - (min_index:max_index)) * coef_current(min_index:max_index).';
function output = bi_round(data_in,LSB_RM,ORI_WIDTH)
% LSB_RM is the bit to lose in LSB
% ORI_WIDTH is the original data width
data = round (data_in / 2^LSB_RM);
output = bi_satu(data,0,ORI_WIDTH - LSB_RM);
function output = bi_trunc_lsb(data_in,LSB_RM,ORI_WIDTH)
% LSB_RM is the bit to lose in LSB
% ORI_WIDTH is the original data width
%2's complement system
output = bitshift((2^ORI_WIDTH*(data_in<0)) + (2^LSB_RM)*floor(data_in/(2^LSB_RM)), -LSB_RM) - (2^(ORI_WIDTH-LSB_RM)) *(data_in<0);
function output = bi_trunc_msb(data_in,MSB_RM,ORI_WIDTH)
% MSB_RM is the bit to lose in LSB
% ORI_WIDTH is the original data width
%2's complement system
data = 2^ORI_WIDTH * (data_in < 0)+ data_in;
erase_num = 2^(ORI_WIDTH - MSB_RM) - 1;
data = bitand(data, erase_num);
output = data - 2^(ORI_WIDTH - MSB_RM)*(bitget(data,ORI_WIDTH - MSB_RM));
function output = bi_satu(data_in,MSB_RM,ORI_WIDTH)
% MSB_RM is the bit to lose in LSB
% ORI_WIDTH is the original data width
%2's complement system
maxdat = 2^(ORI_WIDTH - MSB_RM - 1)-1;
mindat = 2^(ORI_WIDTH - MSB_RM - 1)*(-1);
data_in(data_in > maxdat) = maxdat;
data_in(data_in < mindat) = mindat;
output = data_in;
ld3/dds_vhdl/fir_sim/fir_model.m
+139
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% ================================================================================
% Legal Notice: Copyright (C) 2020 Intel Corporation. All rights reserved.
% Any megafunction design, and related net list (encrypted or decrypted),
% support information, device programming or simulation file, and any other
% associated documentation or information provided by Intel or a partner
% under Intel's Megafunction Partnership Program may be used only to
% program PLD devices (but not masked PLD devices) from Intel. Any other
% use of such megafunction design, net list, support information, device
% programming or simulation file, or any other related documentation or
% information is prohibited for any other purpose, including, but not
% limited to modification, reverse engineering, de-compiling, or use with
% any other silicon devices, unless such use is explicitly licensed under
% a separate agreement with Intel or a megafunction partner. Title to
% the intellectual property, including patents, copyrights, trademarks,
% trade secrets, or maskworks, embodied in any such megafunction design,
% net list, support information, device programming or simulation file, or
% any other related documentation or information provided by Intel or a
% megafunction partner, remains with Intel, the megafunction partner, or
% their respective licensors. No other licenses, including any licenses
% needed under any third party's intellectual property, are provided herein.
% ================================================================================
% Generated on: 06/09/2020 18:16:10
% Generated by: FIR Compiler II 19.1
%---------------------------------------------------------------------------------------------------------
%
% THIS IS A WIZARD GENERATED FILE. DO NOT EDIT THIS FILE!
%
%---------------------------------------------------------------------------------------------------------
clear;
sx = 1;
num_ch = 1;
poly_type = 'single_rate';
dec_fact = 1;
int_fact = 1;
bankcount = 1;
reconfigurable = false;
mode_mapping = [0];
for j = 1:sx
%
%open and read data from file
%
file_name = ['fir_input.txt'];
infile = fopen (file_name, 'r');
input = fscanf(infile, '%d', [1 inf])';
real_data = input(:,1);
data = input(:,1);
bank = zeros(size(data));
for i = 1 : size(input)
mode(i) = mod(i-1,num_ch);
end
fclose(infile);
% array to store output, one row of data for each channel
if (strcmp(poly_type,'single_rate'))
if (floor(length(data)/num_ch)*num_ch~=length(data))
data=data(1:floor(length(data)/num_ch)*num_ch);
end
elseif (strcmp(poly_type,'decimation'))
if (floor(length(data)/num_ch)*num_ch~=length(data))
data=data(1:floor(length(data)/num_ch)*num_ch);
end
end
single_channel_data = cell(num_ch, 1);
single_channel_bank = cell(num_ch, 1);
output = cell(num_ch, 1);
for j = 1: size(data,1);
time_slot = mod(j-1,num_ch);
if (reconfigurable)
cur_mode = mode(j);
channel = mode_mapping(cur_mode+1,time_slot+1)+1;
else
channel = time_slot+1;
end
single_channel_data{channel} = [single_channel_data{channel} data(j)];
single_channel_bank{channel} = [single_channel_bank{channel} bank(j)];
end
for i = 1 : size(single_channel_bank,1)
if not(isempty(single_channel_bank{i}))
for j = 1:length(single_channel_bank{i})
for k = 1:int_fact
bank_int((j-1)*int_fact+k) = single_channel_bank{i}(j);
end
end
single_channel_bank{i} = bank_int;
end
end
% run this output through the model
for i = 1 : num_ch
if(not(isempty(single_channel_data{i})))
output_ch{i} = fir_mlab(single_channel_data{i}, single_channel_bank{i});
output_ch_eaten{i} = output_ch{i};
end
end
% reshape the output_channel so that the is channelwise
limit = length(data)*int_fact/dec_fact;
out = cell(1, 1);
for j = 1: limit;
time_slot = mod(j-1,num_ch);
if (reconfigurable)
cur_mode = mode(max(floor((j*dec_fact)/int_fact),1));
channel = mode_mapping(cur_mode+1,time_slot+1)+1;
else
channel = time_slot+1;
end
out{1} = [out{1} output_ch_eaten{channel}(1)];
output_ch_eaten{channel} = output_ch_eaten{channel}(1,2:end);
end
% Write data out to file
file_name = ['fir_model_output'];
outfile1 = fopen([file_name, '.txt'],'w');
for i=1:length(out{1})
if out{1}(i)>=0
fprintf(outfile1, '%s\n',dec2hex(out{1}(i),10));
else
fprintf(outfile1, '%s\n',dec2hex(2^(10*4)+out{1}(i),10));
end
end
fclose(outfile1);
end
ld3/dds_vhdl/fir_sim/fir_msim.tcl
+176
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## ================================================================================
## Legal Notice: Copyright (C) 1991-2020 Altera Corporation. All rights reserved.
## Any megafunction design, and related net list (encrypted or decrypted),
## support information, device programming or simulation file, and any other
## associated documentation or information provided by Altera or a partner
## under Altera's Megafunction Partnership Program may be used only to
## program PLD devices (but not masked PLD devices) from Altera. Any other
## use of such megafunction design, net list, support information, device
## programming or simulation file, or any other related documentation or
## information is prohibited for any other purpose, including, but not
## limited to modification, reverse engineering, de-compiling, or use with
## any other silicon devices, unless such use is explicitly licensed under
## a separate agreement with Altera or a megafunction partner. Title to
## the intellectual property, including patents, copyrights, trademarks,
## trade secrets, or maskworks, embodied in any such megafunction design,
## net list, support information, device programming or simulation file, or
## any other related documentation or information provided by Altera or a
## megafunction partner, remains with Altera, the megafunction partner, or
## their respective licensors. No other licenses, including any licenses
## needed under any third party's intellectual property, are provided herein.
## ================================================================================
##
transcript on
write transcript fir_transcript
# START MEGAWIZARD INSERT VARIABLES
set top_entity fir
set timing_resolution "1ps"
set core_version 19.1
set device_family "Cyclone V"
set quartus_rootdir C:/intelfpga_lite/19.1/quartus/
# Change to "gate_level" for gate-level sim
set sim_type "rtl"
# END MEGAWIZARD INSERT VARIABLES
set q_sim_lib [file join $quartus_rootdir eda sim_lib]
# Close existing ModelSim simulation
quit -sim
if {[file exists [file join simulation modelsim ${top_entity}.vo]] && [string match "gate_level" $sim_type]} {
puts "Info: Gate Level ${top_entity}.vo found"
set language_ext "vo"
set use_ipfs 1
set flow "gate_level"
} elseif {[file exists [file join simulation modelsim ${top_entity}.vho]] && [string match "gate_level" $sim_type]} {
puts "Info: Gate Level ${top_entity}.vho found"
set language_ext "vho"
set use_ipfs 1
set flow "gate_level"
} else {
puts "Info: RTL simulation."
set use_ipfs 0
set flow "rtl"
}
if {[string match $flow "gate_level"] } {
file copy ${top_entity}_input.txt simulation/modelsim
cd simulation/modelsim
}
regsub {[ ]+} $device_family "" temp_device_family
regsub {[ ]+} $temp_device_family "" temp_device_family2
set device_lib_name [string tolower $temp_device_family2]
set libs [list \
$device_lib_name \
altera \
work]
foreach {lib} $libs {
if {[file exist $lib]} {
catch {eval "file delete -force -- $lib"} fid
puts "file delete command returned $fid\n"
}
if {[file exist $lib] == 0} {
vlib $lib
vmap $lib $lib
}
}
# RTL Simulation
# Compile all required simulation library files
set quartus_libs [list \
altera_mf {altera_mf_components altera_mf} {} {} "$q_sim_lib" \
lpm {220pack 220model} {220model} {} "$q_sim_lib" \
sgate {sgate_pack sgate} {sgate} {} "$q_sim_lib" \
altera_lnsim {altera_lnsim_components} {} {mentor/altera_lnsim_for_vhdl} "$q_sim_lib" \
twentynm {twentynm_atoms twentynm_components} {} {} "$q_sim_lib" \
]
foreach {lib file_vhdl_list file_verilog_list file_sysverilog_list src_files_loc} $quartus_libs {
if {[file exist $lib]} {
catch {eval "file delete -force -- $lib"} fid
puts "file delete command returned $fid\n"
}
if {[file exist $lib] == 0} {
vlib $lib
vmap $lib $lib
}
foreach file_item $file_vhdl_list {
catch {vcom -quiet -explicit -93 -work $lib [file join $src_files_loc ${file_item}.vhd]} err_msg
if {![string match "" $err_msg]} {return $err_msg}
}
foreach file_item $file_verilog_list {
catch {vlog -work $lib [file join $src_files_loc ${file_item}.v]} err_msg
if {![string match "" $err_msg]} {return $err_msg}
}
foreach file_item $file_sysverilog_list {
catch {vlog -work $lib [file join $src_files_loc ${file_item}.sv]} err_msg
if {![string match "" $err_msg]} {return $err_msg}
}
}
vcom -93 -work altera $q_sim_lib/altera_primitives_components.vhd
vcom -93 -work altera $q_sim_lib/altera_primitives.vhd
# Compile all FIR Compiler II RTL files
vlog -work work altera_avalon_sc_fifo.v
vcom -work work dspba_library_package.vhd
vcom -work work dspba_library.vhd
vcom -work work auk_dspip_roundsat_hpfir.vhd
vcom -work work auk_dspip_math_pkg_hpfir.vhd
vcom -work work auk_dspip_lib_pkg_hpfir.vhd
vcom -work work auk_dspip_avalon_streaming_controller_hpfir.vhd
vcom -work work auk_dspip_avalon_streaming_sink_hpfir.vhd
vcom -work work auk_dspip_avalon_streaming_source_hpfir.vhd
set file_list [glob ${top_entity}_rtl*.vhd]
foreach cur_file $file_list {
vcom -work work $cur_file
}
vcom -work work ${top_entity}_ast.vhd
vcom -work work ${top_entity}.vhd
vcom -93 -work work ${top_entity}_tb.vhd
# Prepare simulation command
set vsim_cmd vsim
if {[string match $flow "rtl"]} {
lappend vsim_cmd "-L" "$device_lib_name" "-L" "altera_mf" "-L" "lpm" "-L" "sgate" "-L" "altera" "-L" "altera_lnsim" "-L" "work"
} else {
lappend vsim_cmd "-L" "$device_lib_name" "-L" "altera" "-L" "work"
if {[string match $language_ext "vho"]} {
if {[file exists ${top_entity}_vhd.sdo]} {
lappend vsim_cmd "-sdftyp" "/${top_entity}_tb/DUT=${top_entity}_vhd.sdo"}
}
if {[string match $language_ext "vo"]} {
if {[file exists ${top_entity}_v.sdo]} {
lappend vsim_cmd "-sdftyp" "/${top_entity}_tb/DUT=${top_entity}_v.sdo"}
}
}
lappend vsim_cmd "work.${top_entity}_tb" "-t" "$timing_resolution"
catch { eval $vsim_cmd } vsim_msg
puts $vsim_msg
if {[file exists "wave.do"]} {
do wave.do
} else {
add wave sim:/${top_entity}_tb/*
}
# Start simulation silently
set StdArithNoWarnings 1
run 0 ns
set StdArithNoWarnings 0
catch {run -all} run_msg
puts $run_msg
ld3/dds_vhdl/fir_sim/fir_nativelink.tcl
+58
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## ================================================================================
## Legal Notice: Copyright (C) 2020 Intel Corporation. All rights reserved.
## Any megafunction design, and related net list (encrypted or decrypted),
## support information, device programming or simulation file, and any other
## associated documentation or information provided by Intel or a partner
## under Intel's Megafunction Partnership Program may be used only to
## program PLD devices (but not masked PLD devices) from Intel. Any other
## use of such megafunction design, net list, support information, device
## programming or simulation file, or any other related documentation or
## information is prohibited for any other purpose, including, but not
## limited to modification, reverse engineering, de-compiling, or use with
## any other silicon devices, unless such use is explicitly licensed under
## a separate agreement with Intel or a megafunction partner. Title to
## the intellectual property, including patents, copyrights, trademarks,
## trade secrets, or maskworks, embodied in any such megafunction design,
## net list, support information, device programming or simulation file, or
## any other related documentation or information provided by Intel or a
## megafunction partner, remains with Intel, the megafunction partner, or
## their respective licensors. No other licenses, including any licenses
## needed under any third party's intellectual property, are provided herein.
## ================================================================================
##
# Testbench simulation files
set testbench_files [glob -nocomplain -- *.hex]
set input_files [glob -nocomplain -- *input.txt]
set file_dir [file dirname [info script]]
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
# Set test bench name
set_global_assignment -name EDA_TEST_BENCH_NAME tb -section_id eda_simulation
# Test bench settings
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME DUT -section_id tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME work.fir_tb -section_id tb
set_global_assignment -name EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY work -section_id tb
# Add Testbench files
foreach i $testbench_files {
set_global_assignment -name EDA_TEST_BENCH_FILE $i -section_id tb -library work
}
if {[file exists $file_dir/fir_coef_reload.txt]} {
set_global_assignment -name EDA_TEST_BENCH_FILE $file_dir/fir_coef_reload.txt -section_id tb -library work
}
if {[file exists $file_dir/fir_coef_reload_rtl.txt]} {
set_global_assignment -name EDA_TEST_BENCH_FILE $file_dir/fir_coef_reload_rtl.txt -section_id tb -library work
}
set_global_assignment -name EDA_TEST_BENCH_FILE $file_dir/fir_input.txt -section_id tb -library work
set_global_assignment -name EDA_TEST_BENCH_FILE $file_dir/fir_tb.vhd -section_id tb -library work
# Specify testbench mode for nativelink
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
# Specify active testbench for nativelink
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb -section_id eda_simulation
ld3/dds_vhdl/fir_sim/fir_param.txt
+19
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PhysChanIn : 1
PhysChanOut : 1
ChansPerPhyIn : 1
ChansPerPhyOut : 1
InWidth : 16
InFracWidth : 14
OutWidth : 37
OutFullWidth : 37
OutFracWidth : 28
OutFullFracWidth : 28
nChans : 41
nTaps : 41
clockRate : 100
inRate : 100
interpN : 1
decimN : 1
busDataWidth : 16
bankInWidth : 0
modeWidth : 0
ld3/dds_vhdl/fir_sim/fir_rtl_core.vhd
+1033
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File diff suppressed because it is too large Load Diff
ld3/dds_vhdl/fir_sim/fir_tb.vhd
+472
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-- (C) 2001-2019 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files from any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License Subscription
-- Agreement, Intel FPGA IP License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Intel and sold by
-- Intel or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
entity fir_tb is
constant FIR_INPUT_FILE_c : string := "fir_input.txt";
constant FIR_OUTPUT_FILE_c : string := "fir_output.txt";
constant PHYSCHANIN_c : natural := 1;
constant PHYSCHANOUT_c : natural := 1;
constant INWIDTH_c : natural := 16;
constant OUTWIDTH_c : natural := 37;
constant BANKINWIDTH_c : natural := 0;
constant BANKCOUNT_c : natural := 1;
constant DATA_WIDTH_c : natural := (INWIDTH_c+BANKINWIDTH_c) * PHYSCHANIN_c;
constant OUT_WIDTH_c : natural := OUTWIDTH_c * PHYSCHANOUT_c;
constant NUM_OF_CHANNELS_c : natural := 1;
constant CHANSPERPHYIN_c : natural := 1;
constant CHANSPERPHYOUT_c : natural := 1;
constant LOG2_CHANSPERPHYOUT_c : natural := 0;
constant TDM_FACTOR_c : natural := 1;
constant INVERSE_TDM_FACTOR_c : natural := 1;
constant INVALID_CYCLES_c : natural := 0;
constant INTERP_FACTOR_c : natural := 1;
constant TOTAL_INCHANS_ALLOWED : natural := PHYSCHANIN_c * CHANSPERPHYIN_c;
constant TOTAL_OUTCHANS_ALLOWED : natural := PHYSCHANOUT_c * CHANSPERPHYOUT_c;
constant NUM_OF_TAPS_c : natural := 41;
constant TOTAL_EFF_COEF_c : natural := 41;
constant COEFF_BIT_WIDTH_c : natural := 8;
constant COEFF_BUS_DATA_WIDTH_c : natural := 16;
constant COEFF_BUS_ADDR_WIDTH : natural := 6;
end entity fir_tb;
architecture rtl of fir_tb is
signal ast_sink_data : std_logic_vector (DATA_WIDTH_c-1 downto 0) := (others => '0');
signal ast_source_data : std_logic_vector (OUT_WIDTH_c-1 downto 0);
signal ast_sink_error : std_logic_vector (1 downto 0) := (others => '0');
signal ast_source_error : std_logic_vector (1 downto 0);
signal ast_sink_valid : std_logic := '0';
signal ast_source_valid : std_logic;
signal ast_source_ready : std_logic := '0';
signal clk : std_logic := '0';
signal reset_testbench : std_logic := '1';
signal reset_design : std_logic;
signal eof : std_logic;
signal sink_completed : std_logic := '0';
signal ast_sink_ready : std_logic;
----coef reload ports
signal cnt : natural range 0 to CHANSPERPHYIN_c;
signal push_counter : natural range 0 to CHANSPERPHYIN_c :=0;
constant tclk : time := 10 ns;
constant time_lapse_max : time := 60 us;
signal time_lapse : time;
signal valid_cycles : std_logic := '1';
function div_ceil(a : natural; b : natural) return natural is
variable res : natural := a/b;
begin
if res*b /= a then
res := res +1;
end if;
return res;
end div_ceil;
function to_hex (value : in signed) return string is
constant ne : integer := (value'length+3)/4;
constant NUS : string(2 downto 1) := (others => ' ');
variable pad : std_logic_vector(0 to (ne*4 - value'length) - 1);
variable ivalue : std_logic_vector(0 to ne*4 - 1);
variable result : string(1 to ne);
variable quad : std_logic_vector(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => value(value'high));
end if;
ivalue := pad & std_logic_vector (value);
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hex;
begin
DUT : entity work.fir
port map (
clk => clk,
reset_n => reset_design,
ast_sink_data => ast_sink_data,
ast_source_data => ast_source_data,
ast_sink_valid => ast_sink_valid,
ast_source_valid => ast_source_valid,
ast_sink_error => ast_sink_error,
ast_source_error => ast_source_error
);
-- for example purposes, the ready signal is always asserted.
ast_source_ready <= '1';
ast_sink_ready <= '1';
-- no input error
ast_sink_error <= (others => '0');
-----------------------------------------------------------------------------------------------
-- Read input data from file
-----------------------------------------------------------------------------------------------
source_model : process(clk) is
file in_file : text open read_mode is FIR_INPUT_FILE_c;
variable data_in : integer;
variable bank_in : integer;
variable indata : line;
variable read_data_completed: integer;
variable q, j, j_temp : integer := 0 ;
variable realInChansCount : integer ;
variable totalInChansCount : integer ;
variable idle_cyles : integer := 0 ;
type In_2D is array (PHYSCHANIN_c-1 downto 0, CHANSPERPHYIN_c-1 downto 0) of integer;
variable arrayIn : In_2D;
variable arrayBank : In_2D;
--Debug
variable my_line : line;
begin
if rising_edge(clk) then
if(reset_testbench = '0') then
ast_sink_data <= std_logic_vector(to_signed(0, DATA_WIDTH_c)) after tclk/4;
ast_sink_valid <= '0' after tclk/4;
eof <= '0';
realInChansCount := NUM_OF_CHANNELS_c * INVERSE_TDM_FACTOR_c;
totalInChansCount := TOTAL_INCHANS_ALLOWED;
else
if (sink_completed='0' or eof='0') then
eof <= '0';
if( valid_cycles = '1' and ast_sink_ready = '1') then
if not endfile(in_file) then
if (push_counter=0) then
q := 0;
for k in 0 to PHYSCHANIN_c-1 loop
-- Super-Sample Rate
if (k /= 0) then
j := j + INVERSE_TDM_FACTOR_c;
if (j > PHYSCHANIN_c - 1) then
j_temp := j_temp + 1;
j := j_temp;
end if;
else
j := k;
end if;
for i in 0 to CHANSPERPHYIN_c-1 loop
totalInChansCount := totalInChansCount - 1;
if (realInChansCount > 0) then
realInChansCount := realInChansCount - 1;
readline(in_file, indata);
read(indata, data_in);
arrayIn(j,i) := data_in;
if (BANKINWIDTH_c > 0) then
read(indata, bank_in);
arrayBank(j,i) := bank_in;
end if;
ast_sink_valid <= '1' after tclk/4;
--Debug
--write(my_line, string'(" j = "));
--write(my_line, j);
--write(my_line, string'(" i = "));
--write(my_line, i);
--write(my_line, string'(" Array content = "));
--write(my_line, arrayIn(j,i));
--writeline(output, my_line);
end if;
end loop;
if (totalInChansCount = 0) then
realInChansCount := NUM_OF_CHANNELS_c * INVERSE_TDM_FACTOR_c;
totalInChansCount := TOTAL_INCHANS_ALLOWED;
end if;
end loop;
j_temp := 0;
sink_completed <= '0';
read_data_completed := 1;
end if;
else
eof <='1';
end if;
-- Reorder the input format
-- Expected input format by FIR Compiler II
-- ..., <C2>, <C1>, <C0>, -->
-- ..., <C5>, <C4>, <C3>, -->
-- ..., <C8>, <C7>, <C6>, -->
if (read_data_completed = 1) then
for p in 0 to PHYSCHANIN_c-1 loop
--Debug
--write(my_line, string'(" Push input = "));
--write(my_line,arrayIn(p,q));
--writeline(output, my_line); -- write to display
ast_sink_data(p*(INWIDTH_c+BANKINWIDTH_c)+INWIDTH_c-1 downto (INWIDTH_c+BANKINWIDTH_c)*p) <= std_logic_vector(to_signed(arrayIn(p,q), INWIDTH_c)) after tclk/4;
if (BANKINWIDTH_c > 0) then
ast_sink_data(p*(INWIDTH_c+BANKINWIDTH_c)+(INWIDTH_c+BANKINWIDTH_c)-1 downto (INWIDTH_c+BANKINWIDTH_c)*p+INWIDTH_c) <= std_logic_vector(to_signed(arrayBank(p,q), BANKINWIDTH_c)) after tclk/4;
end if;
end loop;
if ( q < CHANSPERPHYIN_c ) then
q := q + 1;
else
q := 0;
end if;
if ( push_counter < CHANSPERPHYIN_c-1 ) then
push_counter <= push_counter + 1;
else
push_counter <= 0;
read_data_completed := 0;
sink_completed <= '1';
--start invalid cycles if needed
if ( idle_cyles < INVALID_CYCLES_c ) then
valid_cycles <= '0' ;
end if;
end if;
end if;
-- End Reordering and sinking data
else
if ( idle_cyles < INVALID_CYCLES_c ) then
ast_sink_valid <= '0' after tclk/4;
idle_cyles := idle_cyles + 1;
if ( idle_cyles = INVALID_CYCLES_c ) then
valid_cycles <= '1' ;
idle_cyles := 0;
end if;
end if;
ast_sink_data <= ast_sink_data after tclk/4;
end if;
else
eof <= '1';
ast_sink_valid <= '0' after tclk/4;
ast_sink_data <= std_logic_vector(to_signed(0, DATA_WIDTH_c)) after tclk/4;
end if;
end if;
end if;
end process source_model;
---------------------------------------------------------------------------------------------
-- Write FIR output to file
---------------------------------------------------------------------------------------------
sink_model : process(clk) is
file ro_file : text open write_mode is FIR_OUTPUT_FILE_c;
variable rdata : line;
variable y,z,z_temp : integer :=0;
variable realOutChansCount : natural := NUM_OF_CHANNELS_c * INVERSE_TDM_FACTOR_c;
variable totalOutChansCount : natural := TOTAL_OUTCHANS_ALLOWED;
type Out_2D is array (CHANSPERPHYOUT_c-1 downto 0, PHYSCHANOUT_c-1 downto 0) of string(div_ceil(OUTWIDTH_c,4) downto 1);
variable arrayOut : Out_2D;
begin
if rising_edge(clk) then
if(ast_source_valid = '1' and ast_source_ready = '1') then
-- Expected output format from FIR Compiler II
--> <C0>, <C1>, <C2>, ...
--> <C3>, <C4>, <C5>, ...
--> <C6>, <C7>, <C8>, ...
for x in 0 to PHYSCHANOUT_c-1 loop
-- Super-Sample Rate or Interpolation with TDM = 1
-- only interpolation factor is needed for super-sample rate test
if ( PHYSCHANOUT_c > NUM_OF_CHANNELS_c ) then
if (x /= 0) then
z := z + INVERSE_TDM_FACTOR_c * div_ceil(INTERP_FACTOR_c,TDM_FACTOR_c);
if (z > PHYSCHANOUT_c-1) then
z_temp := z_temp + 1;
z := z_temp;
end if;
end if;
else
z := x;
end if;
-- report as hex representation of integer.
arrayOut(y,x) := to_hex(signed(ast_source_data(z*OUTWIDTH_c+OUTWIDTH_c-1 downto OUTWIDTH_c*z)));
end loop;
if (y < CHANSPERPHYOUT_c - 1) then
y := y + 1;
else
y := 0;
z := 0;
z_temp := 0;
for n in 0 to PHYSCHANOUT_c-1 loop
for m in 0 to CHANSPERPHYOUT_c-1 loop
totalOutChansCount := totalOutChansCount - 1;
if (realOutChansCount > 0) then
if (NUM_OF_CHANNELS_c > PHYSCHANOUT_c) then
realOutChansCount := realOutChansCount - 1;
end if;
write(rdata, arrayOut(m,n));
writeline(ro_file, rdata);
end if;
end loop;
end loop;
end if;
if (totalOutChansCount = 0) then
realOutChansCount := NUM_OF_CHANNELS_c * INVERSE_TDM_FACTOR_c;
totalOutChansCount := TOTAL_OUTCHANS_ALLOWED;
end if;
end if;
end if;
end process sink_model;
-------------------------------------------------------------------------------
-- clock generator
-------------------------------------------------------------------------------
clkgen : process
begin -- process clkgen
if eof = '1' and sink_completed = '1' and ast_source_valid = '0' and time_lapse >= time_lapse_max then
clk <= '0';
assert FALSE
report "NOTE: Stimuli ended" severity note;
wait;
elsif time_lapse >= time_lapse_max then
clk <= '0';
assert FALSE
report "ERROR: Reached time_lapse_max without activity, probably simulation is stuck!" severity Error;
wait;
else
clk <= '0';
wait for tclk/2;
clk <= '1';
wait for tclk/2;
end if;
end process clkgen;
monitor_toggling_activity : process(clk, reset_testbench,
ast_source_data, ast_source_valid)
begin
if reset_testbench = '0' then
time_lapse <= 0 ns;
elsif ast_source_data'event or ast_source_valid'event then
time_lapse <= 0 ns;
elsif rising_edge(clk) then
if time_lapse < time_lapse_max then
time_lapse <= time_lapse + tclk;
end if;
end if;
end process monitor_toggling_activity;
-------------------------------------------------------------------------------
-- reset generator
-------------------------------------------------------------------------------
reset_testbench_gen : process
begin -- process resetgen
reset_testbench <= '1';
wait for tclk/4;
reset_testbench <= '0';
wait for tclk*2;
reset_testbench <= '1';
wait;
end process reset_testbench_gen;
reset_design_gen : process
begin -- process resetgen
reset_design <= '1';
wait for tclk/4;
reset_design <= '0';
wait for tclk*2;
reset_design <= '1';
wait for tclk*80;
reset_design <= '1';
wait for tclk*41*2;
reset_design <= '1';
wait;
end process reset_design_gen;
end architecture rtl;
ld3/dds_vhdl/fir_sim/mentor/msim_setup.tcl
+313
View File
@@ -0,0 +1,313 @@
# (C) 2001-2020 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Altera
# Program License Subscription Agreement, Altera MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ----------------------------------------
# Auto-generated simulation script msim_setup.tcl
# ----------------------------------------
# This script provides commands to simulate the following IP detected in
# your Quartus project:
# fir
#
# Altera recommends that you source this Quartus-generated IP simulation
# script from your own customized top-level script, and avoid editing this
# generated script.
#
# To write a top-level script that compiles Altera simulation libraries and
# the Quartus-generated IP in your project, along with your design and
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
# into a new file, e.g. named "mentor.do", and modify the text as directed.
#
# ----------------------------------------
# # TOP-LEVEL TEMPLATE - BEGIN
# #
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
# # construct paths to the files required to simulate the IP in your Quartus
# # project. By default, the IP script assumes that you are launching the
# # simulator from the IP script location. If launching from another
# # location, set QSYS_SIMDIR to the output directory you specified when you
# # generated the IP script, relative to the directory from which you launch
# # the simulator.
# #
# set QSYS_SIMDIR <script generation output directory>
# #
# # Source the generated IP simulation script.
# source $QSYS_SIMDIR/mentor/msim_setup.tcl
# #
# # Set any compilation options you require (this is unusual).
# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
# #
# # Call command to compile the Quartus EDA simulation library.
# dev_com
# #
# # Call command to compile the Quartus-generated IP simulation files.
# com
# #
# # Add commands to compile all design files and testbench files, including
# # the top level. (These are all the files required for simulation other
# # than the files compiled by the Quartus-generated IP simulation script)
# #
# vlog <compilation options> <design and testbench files>
# #
# # Set the top-level simulation or testbench module/entity name, which is
# # used by the elab command to elaborate the top level.
# #
# set TOP_LEVEL_NAME <simulation top>
# #
# # Set any elaboration options you require.
# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
# #
# # Call command to elaborate your design and testbench.
# elab
# #
# # Run the simulation.
# run -a
# #
# # Report success to the shell.
# exit -code 0
# #
# # TOP-LEVEL TEMPLATE - END
# ----------------------------------------
#
# IP SIMULATION SCRIPT
# ----------------------------------------
# If fir is one of several IP cores in your
# Quartus project, you can generate a simulation script
# suitable for inclusion in your top-level simulation
# script by running the following command line:
#
# ip-setup-simulation --quartus-project=<quartus project>
#
# ip-setup-simulation will discover the Altera IP
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# ACDS 19.1 670 win32 2020.06.09.18:16:15
# ----------------------------------------
# Initialize variables
if ![info exists SYSTEM_INSTANCE_NAME] {
set SYSTEM_INSTANCE_NAME ""
} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
}
if ![info exists TOP_LEVEL_NAME] {
set TOP_LEVEL_NAME "fir"
}
if ![info exists QSYS_SIMDIR] {
set QSYS_SIMDIR "./../"
}
if ![info exists QUARTUS_INSTALL_DIR] {
set QUARTUS_INSTALL_DIR "C:/intelfpga_lite/19.1/quartus/"
}
if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
set USER_DEFINED_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_ELAB_OPTIONS] {
set USER_DEFINED_ELAB_OPTIONS ""
}
# ----------------------------------------
# Initialize simulation properties - DO NOT MODIFY!
set ELAB_OPTIONS ""
set SIM_OPTIONS ""
if ![ string match "*-64 vsim*" [ vsim -version ] ] {
} else {
}
# ----------------------------------------
# Copy ROM/RAM files to simulation directory
alias file_copy {
echo "\[exec\] file_copy"
}
# ----------------------------------------
# Create compilation libraries
proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
ensure_lib ./libraries/
ensure_lib ./libraries/work/
vmap work ./libraries/work/
vmap work_lib ./libraries/work/
if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
ensure_lib ./libraries/altera_ver/
vmap altera_ver ./libraries/altera_ver/
ensure_lib ./libraries/lpm_ver/
vmap lpm_ver ./libraries/lpm_ver/
ensure_lib ./libraries/sgate_ver/
vmap sgate_ver ./libraries/sgate_ver/
ensure_lib ./libraries/altera_mf_ver/
vmap altera_mf_ver ./libraries/altera_mf_ver/
ensure_lib ./libraries/altera_lnsim_ver/
vmap altera_lnsim_ver ./libraries/altera_lnsim_ver/
ensure_lib ./libraries/cyclonev_ver/
vmap cyclonev_ver ./libraries/cyclonev_ver/
ensure_lib ./libraries/cyclonev_hssi_ver/
vmap cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver/
ensure_lib ./libraries/cyclonev_pcie_hip_ver/
vmap cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver/
ensure_lib ./libraries/altera/
vmap altera ./libraries/altera/
ensure_lib ./libraries/lpm/
vmap lpm ./libraries/lpm/
ensure_lib ./libraries/sgate/
vmap sgate ./libraries/sgate/
ensure_lib ./libraries/altera_mf/
vmap altera_mf ./libraries/altera_mf/
ensure_lib ./libraries/altera_lnsim/
vmap altera_lnsim ./libraries/altera_lnsim/
ensure_lib ./libraries/cyclonev/
vmap cyclonev ./libraries/cyclonev/
}
# ----------------------------------------
# Compile device library files
alias dev_com {
echo "\[exec\] dev_com"
if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/altera_lnsim_for_vhdl.sv" -work altera_lnsim
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_atoms_ncrypt.v" -work cyclonev
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd" -work cyclonev
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd" -work cyclonev
}
}
# ----------------------------------------
# Compile the design files in correct order
alias com {
echo "\[exec\] com"
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/dspba_library_package.vhd"
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/dspba_library.vhd"
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_math_pkg_hpfir.vhd"
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_lib_pkg_hpfir.vhd"
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_avalon_streaming_controller_hpfir.vhd"
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_avalon_streaming_sink_hpfir.vhd"
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_avalon_streaming_source_hpfir.vhd"
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_roundsat_hpfir.vhd"
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_avalon_sc_fifo.v"
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/fir_rtl_core.vhd"
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/fir_ast.vhd"
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/fir.vhd"
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/fir_tb.vhd"
}
# ----------------------------------------
# Elaborate top level design
alias elab {
echo "\[exec\] elab"
eval vsim -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev $TOP_LEVEL_NAME
}
# ----------------------------------------
# Elaborate the top level design with novopt option
alias elab_debug {
echo "\[exec\] elab_debug"
eval vsim -novopt -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev $TOP_LEVEL_NAME
}
# ----------------------------------------
# Compile all the design files and elaborate the top level design
alias ld "
dev_com
com
elab
"
# ----------------------------------------
# Compile all the design files and elaborate the top level design with -novopt
alias ld_debug "
dev_com
com
elab_debug
"
# ----------------------------------------
# Print out user commmand line aliases
alias h {
echo "List Of Command Line Aliases"
echo
echo "file_copy -- Copy ROM/RAM files to simulation directory"
echo
echo "dev_com -- Compile device library files"
echo
echo "com -- Compile the design files in correct order"
echo
echo "elab -- Elaborate top level design"
echo
echo "elab_debug -- Elaborate the top level design with novopt option"
echo
echo "ld -- Compile all the design files and elaborate the top level design"
echo
echo "ld_debug -- Compile all the design files and elaborate the top level design with -novopt"
echo
echo
echo
echo "List Of Variables"
echo
echo "TOP_LEVEL_NAME -- Top level module name."
echo " For most designs, this should be overridden"
echo " to enable the elab/elab_debug aliases."
echo
echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
echo
echo "QSYS_SIMDIR -- Platform Designer base simulation directory."
echo
echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
echo
echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
echo
echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
echo
echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
echo
echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
}
file_copy
h
ld3/dds_vhdl/fir_sim/synopsys/vcsmx/synopsys_sim.setup
+19
View File
@@ -0,0 +1,19 @@
WORK > DEFAULT
DEFAULT: ./libraries/work/
work: ./libraries/work/
altera_ver: ./libraries/altera_ver/
lpm_ver: ./libraries/lpm_ver/
sgate_ver: ./libraries/sgate_ver/
altera_mf_ver: ./libraries/altera_mf_ver/
altera_lnsim_ver: ./libraries/altera_lnsim_ver/
cyclonev_ver: ./libraries/cyclonev_ver/
cyclonev_hssi_ver: ./libraries/cyclonev_hssi_ver/
cyclonev_pcie_hip_ver: ./libraries/cyclonev_pcie_hip_ver/
altera: ./libraries/altera/
lpm: ./libraries/lpm/
sgate: ./libraries/sgate/
altera_mf: ./libraries/altera_mf/
altera_lnsim: ./libraries/altera_lnsim/
cyclonev: ./libraries/cyclonev/
LIBRARY_SCAN = TRUE
ld3/dds_vhdl/fir_sim/synopsys/vcsmx/vcsmx_setup.sh
+230
View File
@@ -0,0 +1,230 @@
# (C) 2001-2020 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Altera
# Program License Subscription Agreement, Altera MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 19.1 670 win32 2020.06.09.18:16:15
# ----------------------------------------
# vcsmx - auto-generated simulation script
# ----------------------------------------
# This script provides commands to simulate the following IP detected in
# your Quartus project:
# fir
#
# Altera recommends that you source this Quartus-generated IP simulation
# script from your own customized top-level script, and avoid editing this
# generated script.
#
# To write a top-level shell script that compiles Altera simulation libraries
# and the Quartus-generated IP in your project, along with your design and
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
# into a new file, e.g. named "vcsmx_sim.sh", and modify text as directed.
#
# You can also modify the simulation flow to suit your needs. Set the
# following variables to 1 to disable their corresponding processes:
# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
# - SKIP_COM: skip compiling Quartus-generated IP simulation files
# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
#
# ----------------------------------------
# # TOP-LEVEL TEMPLATE - BEGIN
# #
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
# # construct paths to the files required to simulate the IP in your Quartus
# # project. By default, the IP script assumes that you are launching the
# # simulator from the IP script location. If launching from another
# # location, set QSYS_SIMDIR to the output directory you specified when you
# # generated the IP script, relative to the directory from which you launch
# # the simulator. In this case, you must also copy the generated library
# # setup "synopsys_sim.setup" into the location from which you launch the
# # simulator, or incorporate into any existing library setup.
# #
# # Run Quartus-generated IP simulation script once to compile Quartus EDA
# # simulation libraries and Quartus-generated IP simulation files, and copy
# # any ROM/RAM initialization files to the simulation directory.
# #
# # - If necessary, specify any compilation options:
# # USER_DEFINED_COMPILE_OPTIONS
# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
# #
# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
# SKIP_ELAB=1 \
# SKIP_SIM=1 \
# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
# QSYS_SIMDIR=<script generation output directory>
# #
# # Compile all design files and testbench files, including the top level.
# # (These are all the files required for simulation other than the files
# # compiled by the IP script)
# #
# vlogan <compilation options> <design and testbench files>
# #
# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
# # testbench module/entity name.
# #
# # Run the IP script again to elaborate and simulate the top level:
# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
# #
# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
# SKIP_FILE_COPY=1 \
# SKIP_DEV_COM=1 \
# SKIP_COM=1 \
# TOP_LEVEL_NAME="'-top <simulation top>'" \
# QSYS_SIMDIR=<script generation output directory> \
# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
# #
# # TOP-LEVEL TEMPLATE - END
# ----------------------------------------
#
# IP SIMULATION SCRIPT
# ----------------------------------------
# If fir is one of several IP cores in your
# Quartus project, you can generate a simulation script
# suitable for inclusion in your top-level simulation
# script by running the following command line:
#
# ip-setup-simulation --quartus-project=<quartus project>
#
# ip-setup-simulation will discover the Altera IP
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# ACDS 19.1 670 win32 2020.06.09.18:16:15
# ----------------------------------------
# initialize variables
TOP_LEVEL_NAME="fir"
QSYS_SIMDIR="./../../"
QUARTUS_INSTALL_DIR="C:/intelfpga_lite/19.1/quartus/"
SKIP_FILE_COPY=0
SKIP_DEV_COM=0
SKIP_COM=0
SKIP_ELAB=0
SKIP_SIM=0
USER_DEFINED_ELAB_OPTIONS=""
USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
# ----------------------------------------
# overwrite variables - DO NOT MODIFY!
# This block evaluates each command line argument, typically used for
# overwriting variables. An example usage:
# sh <simulator>_setup.sh SKIP_SIM=1
for expression in "$@"; do
eval $expression
if [ $? -ne 0 ]; then
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
exit $?
fi
done
# ----------------------------------------
# initialize simulation properties - DO NOT MODIFY!
ELAB_OPTIONS=""
SIM_OPTIONS=""
if [[ `vcs -platform` != *"amd64"* ]]; then
:
else
:
fi
# ----------------------------------------
# create compilation libraries
mkdir -p ./libraries/work/
mkdir -p ./libraries/altera_ver/
mkdir -p ./libraries/lpm_ver/
mkdir -p ./libraries/sgate_ver/
mkdir -p ./libraries/altera_mf_ver/
mkdir -p ./libraries/altera_lnsim_ver/
mkdir -p ./libraries/cyclonev_ver/
mkdir -p ./libraries/cyclonev_hssi_ver/
mkdir -p ./libraries/cyclonev_pcie_hip_ver/
mkdir -p ./libraries/altera/
mkdir -p ./libraries/lpm/
mkdir -p ./libraries/sgate/
mkdir -p ./libraries/altera_mf/
mkdir -p ./libraries/altera_lnsim/
mkdir -p ./libraries/cyclonev/
# ----------------------------------------
# copy RAM/ROM files to simulation directory
# ----------------------------------------
# compile device library files
if [ $SKIP_DEV_COM -eq 0 ]; then
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v" -work cyclonev
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd" -work cyclonev
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd" -work cyclonev
fi
# ----------------------------------------
# compile design files in correct order
if [ $SKIP_COM -eq 0 ]; then
vhdlan -xlrm $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/dspba_library_package.vhd"
vhdlan -xlrm $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/dspba_library.vhd"
vhdlan -xlrm $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_math_pkg_hpfir.vhd"
vhdlan -xlrm $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_lib_pkg_hpfir.vhd"
vhdlan -xlrm $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_avalon_streaming_controller_hpfir.vhd"
vhdlan -xlrm $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_avalon_streaming_sink_hpfir.vhd"
vhdlan -xlrm $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_avalon_streaming_source_hpfir.vhd"
vhdlan -xlrm $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/auk_dspip_roundsat_hpfir.vhd"
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_avalon_sc_fifo.v"
vhdlan -xlrm $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/fir_rtl_core.vhd"
vhdlan -xlrm $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/fir_ast.vhd"
vhdlan -xlrm $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/fir.vhd"
vhdlan -xlrm $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/fir_tb.vhd"
fi
# ----------------------------------------
# elaborate top level design
if [ $SKIP_ELAB -eq 0 ]; then
vcs -lca -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
fi
# ----------------------------------------
# simulate
if [ $SKIP_SIM -eq 0 ]; then
./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
fi