Add files for FIR and IIR filter - not tested
This commit is contained in:
Imants Pulkstenis
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-- (C) 2001-2019 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions and other
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-- software and tools, and its AMPP partner logic functions, and any output
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-- files from any of the foregoing (including device programming or simulation
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-- files), and any associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License Subscription
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-- Agreement, Intel FPGA IP License Agreement, or other applicable
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-- license agreement, including, without limitation, that your use is for the
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-- sole purpose of programming logic devices manufactured by Intel and sold by
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-- Intel or its authorized distributors. Please refer to the applicable
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-- agreement for further details.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- Alex, 02-10-07, this package declaration results in error at built time on a new machine
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--
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use work.auk_dspip_math_pkg_hpfir.all;
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package auk_dspip_lib_pkg_hpfir is
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--Component names:
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--auk_dspip_atlantic_sink
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--auk_dspip_atlantic_source
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--auk_dspip_interface_controller
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--auk_dspip_avalon_streaming_controller_hpfir
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--auk_dspip_avalon_streaming_controller_pe_fir_91
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--auk_dspip_avalon_streaming_sink_hpfir
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--auk_dspip_avalon_streaming_source_hpfir
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--auk_dspip_delay_fir_91
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--auk_dspip_fastadd_fir_91
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--auk_dspip_fastaddsub_fir_91
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--auk_dspip_pipelined_adder_fir_91
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--auk_dspip_fast_accumulator_fir_91
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--auk_dspip_fifo_pfc_fir_91
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--auk_dspip_fpcompiler_alufp
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--auk_dspip_fpcompiler_aslf
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--auk_dspip_fpcompiler_asrf
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--auk_dspip_fpcompiler_castftox
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--auk_dspip_fpcompiler_castxtof
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--auk_dspip_fpcompiler_clzf
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--auk_dspip_fpcompiler_mulfp
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--auk_dspip_pfc_fir_91
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--auk_dspip_roundsat_fir_91
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component auk_dspip_atlantic_sink is
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generic(
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WIDTH : integer := 16;
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PACKET_SIZE : natural := 4;
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log2packet_size : integer := 2
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);
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port(
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clk : in std_logic;
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reset_n : in std_logic;
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----------------- DESIGN SIDE SIGNALS
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data_available : out std_logic; --goes high when new data is available
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data : out std_logic_vector(WIDTH-1 downto 0);
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sink_ready_ctrl : in std_logic; --the controller will tell
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--the interface whether
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--new input can be accepted.
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sink_stall : out std_logic; --needs to stall the design
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--if no new data is coming
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packet_error : out std_logic_vector (1 downto 0); --this is for SOP and EOP check only.
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--when any of these doesn't behave as
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--expected, the error is flagged.
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send_sop : out std_logic; -- transmit SOP signal to the design.
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-- It only transmits the legal SOP.
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send_eop : out std_logic; -- transmit EOP signal to the design.
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-- It only transmits the legal EOP.
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----------------- ATLANTIC SIDE SIGNALS
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at_sink_ready : out std_logic; --it will be '1' whenever the
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--sink_ready_ctrl signal is high.
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at_sink_valid : in std_logic;
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at_sink_data : in std_logic_vector(WIDTH-1 downto 0);
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at_sink_sop : in std_logic := '0';
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at_sink_eop : in std_logic := '0';
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at_sink_error : in std_logic_vector(1 downto 0) --it indicates to the data source
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--that the SOP and EOP signals
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--are not received as expected.
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);
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end component auk_dspip_atlantic_sink;
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component auk_dspip_atlantic_source is
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generic(
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WIDTH : integer := 16;
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packet_size : natural := 4;
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LOG2packet_size : integer := 2;
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multi_channel : BOOLEAN := TRUE
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);
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port(
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clk : in std_logic;
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reset_n : in std_logic;
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----------------- DESIGN SIDE SIGNALS
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data : in std_logic_vector (WIDTH-1 downto 0);
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data_count : in std_logic_vector (LOG2packet_size-1 downto 0) := (others => '0');
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source_valid_ctrl : in std_logic; --the controller will tell
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--the interface whether
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--new input can be accepted.
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source_stall : out std_logic; --needs to stall the design
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--if no new data is coming
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packet_error : in std_logic_vector (1 downto 0);
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----------------- ATLANTIC SIDE SIGNALS
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at_source_ready : in std_logic;
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at_source_valid : out std_logic;
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at_source_data : out std_logic_vector (WIDTH-1 downto 0);
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at_source_channel : out std_logic_vector (log2packet_size-1 downto 0);
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at_source_error : out std_logic_vector (1 downto 0);
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at_source_sop : out std_logic;
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at_source_eop : out std_logic
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);
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-- Declarations
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end component auk_dspip_atlantic_source;
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component auk_dspip_interface_controller IS
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PORT(
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clk : in std_logic;
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reset : IN std_logic;
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ready : in std_logic;
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sink_packet_error : IN std_logic_vector (1 DOWNTO 0);
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sink_stall : IN std_logic;
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source_stall : IN std_logic;
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valid : IN std_logic;
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reset_design : OUT std_logic;
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reset_n : OUT std_logic;
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sink_ready_ctrl : OUT std_logic;
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source_packet_error : OUT std_logic_vector (1 DOWNTO 0);
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source_valid_ctrl : OUT std_logic;
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stall : OUT std_logic
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);
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-- Declarations
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end component auk_dspip_interface_controller ;
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component auk_dspip_avalon_streaming_controller_hpfir is
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port(
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clk : in std_logic;
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--clk_en : in std_logic := '1';
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reset_n : in std_logic;
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--ready : in std_logic;
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sink_packet_error : in std_logic_vector (1 downto 0);
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--sink_stall : in std_logic;
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source_stall : in std_logic;
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valid : in std_logic;
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reset_design : out std_logic;
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sink_ready_ctrl : out std_logic;
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source_packet_error : out std_logic_vector (1 downto 0);
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source_valid_ctrl : out std_logic;
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stall : out std_logic
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);
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-- Declarations
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end component auk_dspip_avalon_streaming_controller_hpfir;
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component auk_dspip_avalon_streaming_controller_pe_fir_91 is
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generic (
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FIFO_WIDTH_g : natural := 8;
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ENABLE_PIPELINE_DEPTH_g : natural := 0; -- this value should match the depth of the enable pipeline in the core
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FAMILY_g : string := "Stratix II";
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MEM_TYPE_g : string := "Auto"
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);
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port(
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clk : in std_logic;
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clk_en : in std_logic := '1';
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reset_n : in std_logic;
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ready : in std_logic;
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sink_packet_error : in std_logic_vector (1 downto 0);
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sink_stall : in std_logic;
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source_stall : in std_logic;
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valid : in std_logic;
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reset_design : out std_logic;
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sink_ready_ctrl : out std_logic;
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source_packet_error : out std_logic_vector (1 downto 0);
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source_valid_ctrl : out std_logic;
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stall : out std_logic;
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data_in : in std_logic_vector(FIFO_WIDTH_g-1 downto 0);
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data_out : out std_logic_vector(FIFO_WIDTH_g-1 downto 0);
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design_stall : out std_logic
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);
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-- Declarations
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end component auk_dspip_avalon_streaming_controller_pe_fir_91;
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component auk_dspip_avalon_streaming_sink_hpfir is
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generic(
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WIDTH_g : integer := 16;
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DATA_WIDTH : integer := 8;
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DATA_PORT_COUNT : integer := 3;
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PACKET_SIZE_g : natural := 4
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--FIFO_DEPTH_g : natural := 5 --if PFC mode is selected, this generic
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--is used for passing the poly_factor.
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--MIN_DATA_COUNT_g : natural := 2;
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--PFC_MODE_g : boolean := false;
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--SOP_EOP_CALC_g : boolean := false; -- calculate sop and eop rather than
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-- reading value from fifo
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--FAMILY_g : string := "Stratix II";
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--MEM_TYPE_g : string := "Auto"
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);
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port(
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clk : in std_logic;
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reset_n : in std_logic;
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----------------- DESIGN SIDE SIGNALS
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data : out std_logic_vector(WIDTH_g-1 downto 0);
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data_valid : out std_logic_vector(0 downto 0);
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sink_ready_ctrl : in std_logic; --the controller will tell
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--the interface whether
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--new input can be accepted.
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--sink_stall : out std_logic; --needs to stall the design
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--if no new data is coming
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packet_error : out std_logic_vector (1 downto 0); --this is for SOP and EOP check only.
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--when any of these doesn't behave as
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--expected, the error is flagged.
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--send_sop : out std_logic; -- transmit SOP signal to the design.
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-- It only transmits the legal SOP.
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--send_eop : out std_logic; -- transmit EOP signal to the design.
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-- It only transmits the legal EOP.
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----------------- ATLANTIC SIDE SIGNALS
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at_sink_ready : out std_logic; --it will be '1' whenever the
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--sink_ready_ctrl signal is high.
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at_sink_valid : in std_logic;
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at_sink_data : in std_logic_vector(WIDTH_g-1 downto 0);
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at_sink_sop : in std_logic := '0';
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at_sink_eop : in std_logic := '0';
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at_sink_error : in std_logic_vector(1 downto 0) := "00" --it indicates
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--that there is an error in the packet.
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);
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end component auk_dspip_avalon_streaming_sink_hpfir;
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component auk_dspip_avalon_streaming_source_hpfir is
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generic(
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WIDTH_g : integer := 8;
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DATA_WIDTH : integer := 8;
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DATA_PORT_COUNT : integer := 1;
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PACKET_SIZE_g : natural := 2;
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FIFO_DEPTH_g : natural := 0;
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HAVE_COUNTER_g : boolean := false;
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COUNTER_LIMIT_g : natural := 4;
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--MULTI_CHANNEL_g : boolean := true;
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USE_PACKETS : integer := 1;
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--FAMILY_g : string := "Stratix II";
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--MEM_TYPE_g : string := "Auto";
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ENABLE_BACKPRESSURE_g : boolean := true
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);
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port(
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clk : in std_logic;
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reset_n : in std_logic;
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----------------- DESIGN SIDE SIGNALS
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data_in : in std_logic_vector (WIDTH_g-1 downto 0);
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data_count : in std_logic_vector (log2_ceil_one(PACKET_SIZE_g)-1 downto 0) := (others => '0');
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source_valid_ctrl : in std_logic;
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source_stall : out std_logic;
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packet_error : in std_logic_vector (1 downto 0);
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----------------- AVALON_STREAMING SIDE SIGNALS
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at_source_ready : in std_logic;
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at_source_valid : out std_logic;
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at_source_data : out std_logic_vector (WIDTH_g-1 downto 0);
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at_source_channel : out std_logic_vector (log2_ceil_one(PACKET_SIZE_g)-1 downto 0);
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at_source_error : out std_logic_vector (1 downto 0);
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at_source_sop : out std_logic;
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at_source_eop : out std_logic
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);
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-- Declarations
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end component auk_dspip_avalon_streaming_source_hpfir;
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component auk_dspip_roundsat_hpfir is
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generic (
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IN_WIDTH_g : natural := 8; -- i/p data width
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REM_LSB_BIT_g : natural := 2; -- no. of lsb to be removed
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REM_LSB_TYPE_g : string := "trunc"; -- trunc/round
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REM_MSB_BIT_g : natural := 2; -- no. of msb to be removed
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REM_MSB_TYPE_g : string := "trunc" -- trunc/sat
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);
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port (
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clk : in std_logic;
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reset_n : in std_logic;
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enable : in std_logic;
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datain : in std_logic_vector(IN_WIDTH_g-1 downto 0);
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valid : out std_logic;
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dataout : out std_logic_vector(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0)
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);
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end component auk_dspip_roundsat_hpfir;
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component auk_dspip_delay_fir_91 is
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generic (
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WIDTH_g : natural := 8; -- data width
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DELAY_g : natural := 8;
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-- number of clock cycles the input
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-- will be delayed by
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MEMORY_TYPE_g : string := "AUTO";
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-- possible values are "m4k", "m512",
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-- "register", "mram", "auto",
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-- "lutram", "M9K", "M144K".
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-- Any other string will be interpreted
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-- as "auto"
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REGISTER_FIRST_g : natural := 1;
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-- if "1", the first delay is guaranteed
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-- to be in registers
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REGISTER_LAST_g : natural := 1); -- if "1", the last delay is guaranteed
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-- to be in registers
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port (
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clk : in std_logic;
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reset : in std_logic;
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enable : in std_logic; -- global clock enable
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datain : in std_logic_vector(WIDTH_g-1 downto 0);
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dataout : out std_logic_vector(WIDTH_g-1 downto 0)
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);
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end component auk_dspip_delay_fir_91;
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component auk_dspip_fastadd_fir_91 is
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generic (
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INWIDTH_g : natural := 18;
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LABWIDTH_g : natural := 16);
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-- width of lab in selected device ( 10 or 16 in Cyclone,
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-- Cylone II, Stratix and Stratix II. Don't know
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-- Stratix III yet.
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port (
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datain1 : in std_logic_vector(INWIDTH_g-1 downto 0);
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datain2 : in std_logic_vector(INWIDTH_g-1 downto 0);
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clk : in std_logic;
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enable : in std_logic;
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reset : in std_logic;
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dataout : out std_logic_vector(INWIDTH_g downto 0));
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end component auk_dspip_fastadd_fir_91;
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component auk_dspip_fastaddsub_fir_91 is
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generic (
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INWIDTH_g : natural := 18;
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LABWIDTH_g : natural := 16);
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-- width of lab in selected device ( 10 or 16 in Cyclone,
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-- Cylone II, Stratix and Stratix II. Don't know
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-- Stratix III yet.
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port (
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datain1 : in std_logic_vector(INWIDTH_g-1 downto 0);
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datain2 : in std_logic_vector(INWIDTH_g-1 downto 0);
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add_nsub : in std_logic;
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clk : in std_logic;
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enable : in std_logic;
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reset : in std_logic;
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dataout : out std_logic_vector(INWIDTH_g downto 0));
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end component auk_dspip_fastaddsub_fir_91;
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component auk_dspip_pipelined_adder_fir_91 is
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generic (
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INWIDTH_g : natural := 42;
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-- width of lab in selected device ( 10 or 16 in Cyclone,
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-- Cylone II, Stratix and Stratix II.
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-- Alex : should I use 19 bits for Stratix III?
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-- The rational being 10 ALM (2 bits x ALM + the carry chain inside the same LAB for efficiency.
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LABWIDTH_g : natural := 38);
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port (
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datain1 : in std_logic_vector(INWIDTH_g-1 downto 0);
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datain2 : in std_logic_vector(INWIDTH_g-1 downto 0);
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clk : in std_logic;
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enable : in std_logic;
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reset : in std_logic;
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dataout : out std_logic_vector(INWIDTH_g downto 0));
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end component auk_dspip_pipelined_adder_fir_91;
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component auk_dspip_fast_accumulator_fir_91 is
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generic (
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DATA_WIDTH_g : natural := 42;
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-- width of lab in selected device ( 10 or 16 in Cyclone,
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-- Cylone II, Stratix and Stratix II.
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-- for Stratix III is 20 so labwidth should be set to 18.
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-- The rational being 10 ALM (2 bits x ALM + the carry chain inside the same LAB for efficiency.
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LABWIDTH_g : natural := 38;
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NUM_OF_CHANNELS_g : natural := 1;
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ACCUM_OUT_WIDTH_g : natural := 48;
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ACCUM_MEM_TYPE_g : string := "auto");
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port (
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reset : in std_logic;
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clk : in std_logic;
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enb : in std_logic;
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add_to_zero : in std_logic;
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datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0);
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datao : out std_logic_vector(ACCUM_OUT_WIDTH_g-1 downto 0));
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end component auk_dspip_fast_accumulator_fir_91;
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||||
|
||||
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component auk_dspip_fifo_pfc_fir_91 is
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generic (
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NUM_CHANNELS_g : integer := 5;
|
||||
POLY_FACTOR_g : integer := 3;
|
||||
DATA_WIDTH_g : integer := 16;
|
||||
ALMOST_FULL_VALUE_g : integer := 2;
|
||||
RAM_TYPE_g : string := "AUTO";
|
||||
CALCULATE_USED_WORDS_ONCE : boolean := true
|
||||
);
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||||
port (
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||||
|
||||
datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0);
|
||||
datao : out std_logic_vector(DATA_WIDTH_g-1 downto 0);
|
||||
channel_out : out std_logic_vector(log2_ceil(NUM_CHANNELS_g)-1 downto 0);
|
||||
used_w : out std_logic_vector(log2_ceil(POLY_FACTOR_g * NUM_CHANNELS_g)+1 downto 0);
|
||||
|
||||
wrreq : in std_logic;
|
||||
rdreq : in std_logic;
|
||||
almost_full : out std_logic;
|
||||
empty : out std_logic;
|
||||
sclr : in std_logic;
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
enable : in std_logic
|
||||
);
|
||||
end component auk_dspip_fifo_pfc_fir_91;
|
||||
component auk_dspip_fpcompiler_alufp is
|
||||
port (
|
||||
sysclk : in std_logic;
|
||||
reset : in std_logic;
|
||||
enable : in std_logic;
|
||||
addsub : in std_logic;
|
||||
aa : in std_logic_vector (42 downto 1);
|
||||
aasat, aazip : in std_logic;
|
||||
bb : in std_logic_vector (42 downto 1);
|
||||
bbsat, bbzip : in std_logic;
|
||||
cc : out std_logic_vector (42 downto 1);
|
||||
ccsat, cczip : out std_logic
|
||||
);
|
||||
end component auk_dspip_fpcompiler_alufp;
|
||||
component auk_dspip_fpcompiler_aslf is
|
||||
port (
|
||||
inbus : in std_logic_vector (32 downto 1);
|
||||
shift : in std_logic_vector (5 downto 1);
|
||||
|
||||
outbus : out std_logic_vector (32 downto 1)
|
||||
);
|
||||
end component auk_dspip_fpcompiler_aslf;
|
||||
component auk_dspip_fpcompiler_asrf is
|
||||
port (
|
||||
inbus : in std_logic_vector (32 downto 1);
|
||||
shift : in std_logic_vector (5 downto 1);
|
||||
|
||||
outbus : out std_logic_vector (32 downto 1)
|
||||
);
|
||||
end component auk_dspip_fpcompiler_asrf;
|
||||
|
||||
component auk_dspip_fpcompiler_castftox is
|
||||
port (
|
||||
aa : in std_logic_vector (32 downto 1);
|
||||
cc : out std_logic_vector (42 downto 1);
|
||||
ccsat, cczip : out std_logic
|
||||
);
|
||||
end component auk_dspip_fpcompiler_castftox;
|
||||
|
||||
component auk_dspip_fpcompiler_castxtof is
|
||||
port (
|
||||
sysclk : in std_logic;
|
||||
reset : in std_logic;
|
||||
enable : in std_logic;
|
||||
aa : in std_logic_vector (42 downto 1);
|
||||
aasat, aazip : in std_logic;
|
||||
cc : out std_logic_vector (32 downto 1)
|
||||
);
|
||||
end component auk_dspip_fpcompiler_castxtof;
|
||||
|
||||
component auk_dspip_fpcompiler_clzf is
|
||||
port (
|
||||
frac : in std_logic_vector (32 downto 1);
|
||||
count : out std_logic_vector (5 downto 1)
|
||||
);
|
||||
end component auk_dspip_fpcompiler_clzf;
|
||||
component auk_dspip_fpcompiler_mulfp is
|
||||
port (
|
||||
sysclk : in std_logic;
|
||||
reset : in std_logic;
|
||||
enable : in std_logic;
|
||||
aa : in std_logic_vector (42 downto 1);
|
||||
aasat, aazip : in std_logic;
|
||||
bb : in std_logic_vector (42 downto 1);
|
||||
bbsat, bbzip : in std_logic;
|
||||
cc : out std_logic_vector (42 downto 1);
|
||||
ccsat, cczip : out std_logic
|
||||
);
|
||||
end component auk_dspip_fpcompiler_mulfp;
|
||||
|
||||
component auk_dspip_pfc_fir_91 is
|
||||
generic (
|
||||
NUM_CHANNELS_g : integer := 5;
|
||||
POLY_FACTOR_g : integer := 3;
|
||||
DATA_WIDTH_g : integer := 16;
|
||||
RAM_TYPE_g : string := "AUTO"
|
||||
);
|
||||
port (
|
||||
|
||||
datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0);
|
||||
datao : out std_logic_vector(DATA_WIDTH_g-1 downto 0);
|
||||
channel_out : out std_logic_vector(log2_ceil(NUM_CHANNELS_g)-1 downto 0);
|
||||
|
||||
in_valid : in std_logic;
|
||||
out_valid : out std_logic;
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
enable : in std_logic
|
||||
);
|
||||
end component auk_dspip_pfc_fir_91;
|
||||
|
||||
|
||||
component auk_dspip_roundsat_fir_91 is
|
||||
generic (
|
||||
IN_WIDTH_g : natural := 8; -- data width
|
||||
OUT_WIDTH_g : natural := 8; -- data width
|
||||
ROUNDING_TYPE_g : string := "TRUNCATE_LOW"
|
||||
);
|
||||
|
||||
port (
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
enable : in std_logic; -- global clock enable
|
||||
datain : in std_logic_vector(IN_WIDTH_g-1 downto 0);
|
||||
dataout : out std_logic_vector(OUT_WIDTH_g-1 downto 0));
|
||||
end component auk_dspip_roundsat_fir_91;
|
||||
|
||||
component auk_dspip_avalon_streaming_block_source_fir_91 is
|
||||
generic (
|
||||
MAX_BLK_g : natural;
|
||||
DATAWIDTH_g : natural);
|
||||
port (
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
in_blk : in std_logic_vector(log2_ceil(MAX_BLK_g) downto 0);
|
||||
in_valid : in std_logic;
|
||||
source_stall : out std_logic;
|
||||
in_data : in std_logic_vector(DATAWIDTH_g - 1 downto 0);
|
||||
source_valid : out std_logic;
|
||||
source_ready : in std_logic;
|
||||
source_sop : out std_logic;
|
||||
source_eop : out std_logic;
|
||||
source_data : out std_logic_vector(DATAWIDTH_g - 1 downto 0));
|
||||
end component auk_dspip_avalon_streaming_block_source_fir_91;
|
||||
|
||||
component auk_dspip_avalon_streaming_block_sink_fir_91 is
|
||||
generic (
|
||||
MAX_BLK_g : natural;
|
||||
STALL_g : natural;
|
||||
DATAWIDTH_g : natural;
|
||||
-- this generic is specific for the FFT.
|
||||
NUM_STAGES_g : natural);
|
||||
port (
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
in_blk : in std_logic_vector(log2_ceil(MAX_BLK_g) downto 0);
|
||||
in_sop : in std_logic;
|
||||
in_eop : in std_logic;
|
||||
in_inverse : in std_logic;
|
||||
sink_valid : in std_logic;
|
||||
sink_ready : out std_logic;
|
||||
source_stall : in std_logic;
|
||||
in_data : in std_logic_vector(DATAWIDTH_g - 1 downto 0);
|
||||
processing : in std_logic;
|
||||
in_error : in std_logic_vector(1 downto 0);
|
||||
out_error : out std_logic_vector(1 downto 0);
|
||||
out_valid : out std_logic;
|
||||
out_sop : out std_logic;
|
||||
out_eop : out std_logic;
|
||||
out_data : out std_logic_vector(DATAWIDTH_g - 1 downto 0);
|
||||
curr_blk : out std_logic_vector(log2_ceil(MAX_BLK_g) downto 0);
|
||||
-- these are specific to the FFT, no effort has been made to optimize!
|
||||
curr_pwr_2 : out std_logic;
|
||||
curr_inverse : out std_logic;
|
||||
curr_input_sel : out std_logic_vector(NUM_STAGES_g - 1 downto 0));
|
||||
end component auk_dspip_avalon_streaming_block_sink_fir_91;
|
||||
|
||||
|
||||
|
||||
end package auk_dspip_lib_pkg_hpfir;
|
||||
Reference in New Issue
Block a user