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Task1 done. Code debuging

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Imants Pulkstenis
2020-02-16 12:20:58 +02:00
parent 4eb5c37b4f
commit 609a9292b3
2 changed files with 28 additions and 27 deletions
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ps2/ps02q/ps02.qsf
+11 -9
View File
@@ -37,22 +37,24 @@
# -------------------------------------------------------------------------- # # -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V" set_global_assignment -name FAMILY "Cyclone 10 GX"
set_global_assignment -name DEVICE 5CGXFC5C6F27C7 set_global_assignment -name DEVICE 10CX220YF780I5G
set_global_assignment -name TOP_LEVEL_ENTITY ps02 set_global_assignment -name TOP_LEVEL_ENTITY ps02
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:44:46 FEBRUARY 25, 2017" set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:44:46 FEBRUARY 25, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition" set_global_assignment -name LAST_QUARTUS_VERSION "19.4.0 Pro Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
# Obsolete assignment in <Version 19.4> "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
"
# Obsolete assignment in <Version 19.4> "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
"
# Obsolete assignment in <Version 19.4> "set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
" "
set_global_assignment -name VHDL_FILE ps02.vhd
# Obsolete assignment in <Version 19.4> "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top" # Obsolete assignment in <Version 19.4> "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name VERILOG_FILE ps02.v
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name VHDL_FILE alu.vhd
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
ps2/ps02q/ps02.v
+15 -16
View File
@@ -27,38 +27,37 @@ module ps02 #( parameter
input clk, input clk,
input rst, input rst,
output [data_width - 1:0] R, output [data_width - 1:0] R,
output flag); output flag
); );
//define inside of the module //define inside of the module
//define inside use signals //define inside use signals
wire [data_width - 1:0] A; wire [data_width - 1:0] A;
wire [data_width - 1:0] B; wire [data_width - 1:0] B;
wire [3:0] op; wire [3:0] op;
//component declaration for A, B, op signal generator //component declaration for A, B, op signal generator
//port map for A, B, op signal generator //port map for A, B, op signal generator
name_of_unit #( ps02_siggen #(
.data_width(data_width) .data_width(data_width)
) ps02_siggen ( ) name_of_unit (
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
.A(A), .A(A),
.B(B), .B(B),
.op(op) .op(op)
); );
//component declaration for alu (TASK 1) //component declaration for alu (TASK 1)
//port map for ALU (TASK 1) //port map for ALU (TASK 1)
name_of_alu_unit #( alu #(
.data_width(data_width) .data_width(data_width)
) alu ( ) name_of_alu_unit (
.clk(clk), .clk(clk),
.rst(rst), .A(A),
.A(A), .B(B),
.B(B), .op(op),
.op(op),
.R(R), .R(R),
.flag(flag) .flag(flag)
); );