From 609a9292b34d188b38250061f6e20fce6f020125 Mon Sep 17 00:00:00 2001 From: Imants Pulkstenis Date: Sun, 16 Feb 2020 12:20:58 +0200 Subject: [PATCH] Task1 done. Code debuging --- ps2/ps02q/ps02.qsf | 24 +++++++++++++----------- ps2/ps02q/ps02.v | 31 +++++++++++++++---------------- 2 files changed, 28 insertions(+), 27 deletions(-) diff --git a/ps2/ps02q/ps02.qsf b/ps2/ps02q/ps02.qsf index 819b6d9..f406ced 100644 --- a/ps2/ps02q/ps02.qsf +++ b/ps2/ps02q/ps02.qsf @@ -37,22 +37,24 @@ # -------------------------------------------------------------------------- # -set_global_assignment -name FAMILY "Cyclone V" -set_global_assignment -name DEVICE 5CGXFC5C6F27C7 +set_global_assignment -name FAMILY "Cyclone 10 GX" +set_global_assignment -name DEVICE 10CX220YF780I5G set_global_assignment -name TOP_LEVEL_ENTITY ps02 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:44:46 FEBRUARY 25, 2017" -set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition" +set_global_assignment -name LAST_QUARTUS_VERSION "19.4.0 Pro Edition" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation -set_global_assignment -name VHDL_FILE alu.vhd -set_global_assignment -name VHDL_FILE ps02.vhd -set_global_assignment -name VHDL_FILE ps02_siggen.vhd -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +# Obsolete assignment in "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top " +# Obsolete assignment in "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top " +# Obsolete assignment in "set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top " +# Obsolete assignment in "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top" +set_global_assignment -name VERILOG_FILE ps02.v +set_global_assignment -name VHDL_FILE alu.vhd +set_global_assignment -name VHDL_FILE ps02_siggen.vhd +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" diff --git a/ps2/ps02q/ps02.v b/ps2/ps02q/ps02.v index ec19565..4e5229f 100644 --- a/ps2/ps02q/ps02.v +++ b/ps2/ps02q/ps02.v @@ -27,38 +27,37 @@ module ps02 #( parameter input clk, input rst, output [data_width - 1:0] R, - output flag); + output flag ); //define inside of the module - //define inside use signals + //define inside use signals wire [data_width - 1:0] A; wire [data_width - 1:0] B; wire [3:0] op; - //component declaration for A, B, op signal generator + //component declaration for A, B, op signal generator //port map for A, B, op signal generator -name_of_unit #( +ps02_siggen #( .data_width(data_width) - ) ps02_siggen ( + ) name_of_unit ( .clk(clk), - .rst(rst), - .A(A), - .B(B), - .op(op) + .rst(rst), + .A(A), + .B(B), + .op(op) ); - //component declaration for alu (TASK 1) + //component declaration for alu (TASK 1) //port map for ALU (TASK 1) -name_of_alu_unit #( +alu #( .data_width(data_width) - ) alu ( + ) name_of_alu_unit ( .clk(clk), - .rst(rst), - .A(A), - .B(B), - .op(op), + .A(A), + .B(B), + .op(op), .R(R), .flag(flag) );