summ not finished

ld3/dds_vhdl/sin_gen.qsf

@@ -39,12 +39,10 @@
 
 set_global_assignment -name FAMILY "Cyclone V"
 set_global_assignment -name DEVICE 5CGXFC7C7F23C8
-set_global_assignment -name TOP_LEVEL_ENTITY sin_gen
+set_global_assignment -name TOP_LEVEL_ENTITY sin_gen_sum
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:16:23  MARCH 21, 2018"
 set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
-set_global_assignment -name VHDL_FILE sin_gen_tb.vhd
-set_global_assignment -name VHDL_FILE sin_gen.vhd
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
@@ -53,6 +51,9 @@ set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
 set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
 set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name VHDL_FILE sin_gen_sum.vhd
+set_global_assignment -name VHDL_FILE sin_gen_tb.vhd
+set_global_assignment -name VHDL_FILE sin_gen.vhd
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

ld3/dds_vhdl/sin_gen_sum.vhd

@@ -24,8 +24,8 @@ entity sin_gen_sum is
     (
         phase_width 						: integer := 9;
         data_width							: integer := 16;
-        phase_incr_one                      : integer := 16;
+        phase_incr_one                      : integer := 37;
-        phase_incr_two                      : integer := 16
+        phase_incr_two                      : integer := 57
     );
     port
     (
@@ -40,7 +40,9 @@ entity sin_gen_sum is
 --define inside of the module
 architecture behavioral of sin_gen_sum is
     --define inside use signals
-
+    signal signal_out_one					   : std_Logic_vector(data_width - 1 downto 0) := (others => '0');
+    signal signal_out_two   					: std_Logic_vector(data_width - 1 downto 0) := (others => '0');
+	 signal signal_summ   						: std_Logic_vector(data_width downto 0) := (others => '0'); --  17bit word
     
     --define components to use
 	component sin_gen is
@@ -54,14 +56,17 @@ architecture behavioral of sin_gen_sum is
             clk 								: in std_logic;	--100mhz clock
             rst									: in std_logic;	--rst
             phase_incr							: in std_Logic_vector(phase_width - 1 downto 0); --"frequency"
-            phase_out							: out std_Logic_vector(phase_width - 1 downto 0);
+            --phase_out							: out std_Logic_vector(phase_width - 1 downto 0);
             signal_out							: out std_Logic_vector(data_width - 1 downto 0)
         );
         end component;
 
 begin	--define the operation of the module!
+	--signal output 
+	signal_out <= std_logic_Vector(signal_summ(data_width  downto 1));
 
-dds_vhdl_one : sin_gen 
+
+sin_gen_one : sin_gen 
 generic map
 (
     phase_width 						=> phase_width,
@@ -71,10 +76,34 @@ port map
 (
     clk 							    	=> clk,
     rst									=> rst,
-    phase_incr							=> phase_incr,
+    phase_incr							=> std_logic_Vector(To_unsigned(phase_incr_one,phase_width)),
-    phase_out							=> phase_out,
+    --phase_out						=> phase_out,
-    signal_out							=> signal_out
+    signal_out							=> signal_out_one
 );
 
+sin_gen_two : sin_gen 
+generic map
+(
+    phase_width 						=> phase_width,
+    data_width							=> data_width
+)
+port map
+(
+    clk 							    	=> clk,
+    rst									=> rst,
+    phase_incr							=> std_logic_Vector(To_unsigned(phase_incr_two,phase_width)),
+    --phase_out						=> phase_out,
+    signal_out							=> signal_out_two
+);
+
+	--adder
+	process(clk)
+	begin
+		if rising_edge(clk) then
+				signal_summ <= signed(signal_out_one) + signed(signal_out_two);
+		end if;
+	end process;
+
+
 
 end behavioral;

ld3/table_gen.m

@@ -0,0 +1,70 @@
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 
+% Author - Imants Pulkstenis
+% Date - 02.05.2020
+% Project name - Lab work No.3
+% Module name - LookUpTable generator
+%
+% Detailed module description:
+% This file generates lock up table with SIN and COS values
+%
+% Revision:
+% A - initial design (copy from PS3)
+% B - 
+% C - 
+%
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+clear;
+word_lenght = 16;
+table_size = 9;   % 2^n
+x = linspace(0, (2*pi - 2*pi/2^table_size) , 2^table_size);
+sin_x = sin(x);
+sin_x = round(sin_x * 2^word_lenght) / 2^word_lenght;   % round values
+
+cos_x = cos(x);
+cos_x = round(cos_x * 2^word_lenght) / 2^word_lenght;   % round values
+
+%% Print values in HEX
+hex_sin = [];
+hex_cos = [];
+for i=1:2^table_size
+    a = sfi(sin_x(i),word_lenght,word_lenght-2);
+    b = sfi(cos_x(i),word_lenght,word_lenght-2);
+    hex_sin = [hex_sin; a.bin];
+    hex_cos = [hex_cos; b.bin];
+end
+%hex_sin,
+%hex_cos,
+
+fid = fopen('lookuptable.v', 'wt');
+    fprintf(fid, 'module lookuptable #( parameter    phase_width = %d,  data_width	= %d)(\n', table_size, word_lenght);
+    fprintf(fid, '\tinput               [phase_width - 1 :0]  phase,\n');
+    fprintf(fid, '\toutput     reg      [data_width - 1 :0]  sin,\n');
+    fprintf(fid, '\toutput     reg      [data_width - 1 :0]  cos);\n');
+    
+%    fprintf(fid, 'reg [%d :0]      sin  = %d''h0;    \n', word_lenght-1,word_lenght);
+    fprintf(fid, 'always@* begin\n');
+    fprintf(fid, 'case (phase[phase_width - 1 : 0])\n');
+    
+for i=1:length(hex_sin) 
+    temp = hex_sin(i,1:word_lenght);
+        fprintf(fid, '\t%d''d%d : sin[data_width - 1 : 0] <= %d''b%s;\n',table_size, i-1  ,word_lenght, hex_sin(i,1:word_lenght) );
+end
+    fprintf(fid, '\tdefault   : sin[data_width - 1 : 0] <= %d''b%s;\n ',word_lenght,  hex_sin(1,1:word_lenght) );
+    fprintf(fid, 'endcase\n');
+    fprintf(fid, 'end\n');
+    fprintf(fid, ' \n');
+
+    fprintf(fid, 'always@* begin\n');
+    fprintf(fid, 'case (phase[phase_width - 1 : 0])\n');
+    
+for i=1:length(hex_cos) 
+    temp = hex_cos(i,1:word_lenght);
+        fprintf(fid, '\t%d''d%d : cos[data_width - 1 : 0] <= %d''b%s;\n',table_size, i-1 ,  word_lenght, hex_cos(i,1:word_lenght) );
+end
+    fprintf(fid, '\tdefault   : cos[data_width - 1 : 0] <= %d''b%s;\n ',word_lenght,  hex_cos(1,1:word_lenght) );
+    fprintf(fid, 'endcase\n');
+    fprintf(fid, 'end\n');
+    fprintf(fid, 'endmodule');
+    
+disp('Text files write done');disp(' ');
+fclose(fid);