summ not finished

ld3/dds_vhdl/sin_gen_sum.vhd

@@ -24,8 +24,8 @@ entity sin_gen_sum is
     (
         phase_width 						: integer := 9;
         data_width							: integer := 16;
-        phase_incr_one                      : integer := 16;
-        phase_incr_two                      : integer := 16
+        phase_incr_one                      : integer := 37;
+        phase_incr_two                      : integer := 57
     );
     port
     (
@@ -40,7 +40,9 @@ entity sin_gen_sum is
 --define inside of the module
 architecture behavioral of sin_gen_sum is
     --define inside use signals
-
+    signal signal_out_one					   : std_Logic_vector(data_width - 1 downto 0) := (others => '0');
+    signal signal_out_two   					: std_Logic_vector(data_width - 1 downto 0) := (others => '0');
+	 signal signal_summ   						: std_Logic_vector(data_width downto 0) := (others => '0'); --  17bit word
     
     --define components to use
 	component sin_gen is
@@ -54,14 +56,17 @@ architecture behavioral of sin_gen_sum is
             clk 								: in std_logic;	--100mhz clock
             rst									: in std_logic;	--rst
             phase_incr							: in std_Logic_vector(phase_width - 1 downto 0); --"frequency"
-            phase_out							: out std_Logic_vector(phase_width - 1 downto 0);
+            --phase_out							: out std_Logic_vector(phase_width - 1 downto 0);
             signal_out							: out std_Logic_vector(data_width - 1 downto 0)
         );
         end component;
 
 begin	--define the operation of the module!
+	--signal output 
+	signal_out <= std_logic_Vector(signal_summ(data_width  downto 1));
 
-dds_vhdl_one : sin_gen 
+
+sin_gen_one : sin_gen 
 generic map
 (
     phase_width 						=> phase_width,
@@ -69,12 +74,36 @@ generic map
 )
 port map
 (
-    clk 							    => clk,
+    clk 							    	=> clk,
     rst									=> rst,
-    phase_incr							=> phase_incr,
-    phase_out							=> phase_out,
-    signal_out							=> signal_out
+    phase_incr							=> std_logic_Vector(To_unsigned(phase_incr_one,phase_width)),
+    --phase_out						=> phase_out,
+    signal_out							=> signal_out_one
 );
 
+sin_gen_two : sin_gen 
+generic map
+(
+    phase_width 						=> phase_width,
+    data_width							=> data_width
+)
+port map
+(
+    clk 							    	=> clk,
+    rst									=> rst,
+    phase_incr							=> std_logic_Vector(To_unsigned(phase_incr_two,phase_width)),
+    --phase_out						=> phase_out,
+    signal_out							=> signal_out_two
+);
+
+	--adder
+	process(clk)
+	begin
+		if rising_edge(clk) then
+				signal_summ <= signed(signal_out_one) + signed(signal_out_two);
+		end if;
+	end process;
+
+
 
 end behavioral;