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summ not finished

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This commit is contained in:
Imants Pulkstenis
2020-06-09 01:03:07 +03:00
parent 13a5336975
commit 56e16842e4
4 changed files with 112 additions and 12 deletions
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ld3/dds_vhdl/sin_gen.qsf
+4 -3
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@@ -39,12 +39,10 @@
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CGXFC7C7F23C8
set_global_assignment -name TOP_LEVEL_ENTITY sin_gen
set_global_assignment -name TOP_LEVEL_ENTITY sin_gen_sum
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:16:23 MARCH 21, 2018"
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
set_global_assignment -name VHDL_FILE sin_gen_tb.vhd
set_global_assignment -name VHDL_FILE sin_gen.vhd
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
@@ -53,6 +51,9 @@ set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VHDL_FILE sin_gen_sum.vhd
set_global_assignment -name VHDL_FILE sin_gen_tb.vhd
set_global_assignment -name VHDL_FILE sin_gen.vhd
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
ld3/dds_vhdl/sin_gen.qws
BIN
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ld3/dds_vhdl/sin_gen_sum.vhd
+38 -9
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@@ -24,8 +24,8 @@ entity sin_gen_sum is
(
phase_width : integer := 9;
data_width : integer := 16;
phase_incr_one : integer := 16;
phase_incr_two : integer := 16
phase_incr_one : integer := 37;
phase_incr_two : integer := 57
);
port
(
@@ -40,7 +40,9 @@ entity sin_gen_sum is
--define inside of the module
architecture behavioral of sin_gen_sum is
--define inside use signals
signal signal_out_one : std_Logic_vector(data_width - 1 downto 0) := (others => '0');
signal signal_out_two : std_Logic_vector(data_width - 1 downto 0) := (others => '0');
signal signal_summ : std_Logic_vector(data_width downto 0) := (others => '0'); -- 17bit word
--define components to use
component sin_gen is
@@ -54,14 +56,17 @@ architecture behavioral of sin_gen_sum is
clk : in std_logic; --100mhz clock
rst : in std_logic; --rst
phase_incr : in std_Logic_vector(phase_width - 1 downto 0); --"frequency"
phase_out : out std_Logic_vector(phase_width - 1 downto 0);
--phase_out : out std_Logic_vector(phase_width - 1 downto 0);
signal_out : out std_Logic_vector(data_width - 1 downto 0)
);
end component;
begin --define the operation of the module!
--signal output
signal_out <= std_logic_Vector(signal_summ(data_width downto 1));
dds_vhdl_one : sin_gen
sin_gen_one : sin_gen
generic map
(
phase_width => phase_width,
@@ -69,12 +74,36 @@ generic map
)
port map
(
clk => clk,
clk => clk,
rst => rst,
phase_incr => phase_incr,
phase_out => phase_out,
signal_out => signal_out
phase_incr => std_logic_Vector(To_unsigned(phase_incr_one,phase_width)),
--phase_out => phase_out,
signal_out => signal_out_one
);
sin_gen_two : sin_gen
generic map
(
phase_width => phase_width,
data_width => data_width
)
port map
(
clk => clk,
rst => rst,
phase_incr => std_logic_Vector(To_unsigned(phase_incr_two,phase_width)),
--phase_out => phase_out,
signal_out => signal_out_two
);
--adder
process(clk)
begin
if rising_edge(clk) then
signal_summ <= signed(signal_out_one) + signed(signal_out_two);
end if;
end process;
end behavioral;