Task 2 - done

ps2/ps02q/alu.v

@@ -23,11 +23,11 @@
 //Entity declaration [part 3 of the Verilog file].
 module alu #( parameter
 	data_width = 32
-)
+)(
 	input                                   clk,
 	input signed        [data_width - 1:0]  A,
 	input signed        [data_width - 1:0]  B,
-	input unsigned      [3:0]               op,
+	input               [3:0]               op,
 	output signed       [data_width - 1:0]  R,
 	output                                  flag);
 
@@ -62,7 +62,7 @@ always@(posedge clk) begin
     endcase
 end
 
-assign R    = reg_R(data_width - 1:0);
+assign R    = reg_R[data_width - 1:0];
 assign flag = (reg_R[data_width]==1'b1) ? 1'b1 : 1'b0; //optional
 
 endmodule

ps2/ps02q/ps02.qsf

@@ -53,8 +53,8 @@ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulati
 "
 # Obsolete assignment in <Version 19.4> "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 "
-# Obsolete assignment in <Version 19.4> "set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-"
-# Obsolete assignment in <Version 19.4> "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top"
 # Obsolete assignment in <Version 19.4> "set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 "
+# Obsolete assignment in <Version 19.4> "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top"
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"

ps2/ps02q/ps02.v

@@ -34,7 +34,7 @@ module ps02 #( parameter
 	 //define inside use signals
 	wire signed     [data_width - 1:0]      A;
 	wire signed     [data_width - 1:0]      B;
-	wire unsigned   [3:0]                   op;
+	wire    			 [3:0]                   op;
 	
     //component declaration for A, B, op signal generator
     //port map for A, B, op signal generator