From 3c38cb75a84699c4e58f8f3a4a06261231fa070d Mon Sep 17 00:00:00 2001 From: Imants Pulkstenis Date: Sun, 16 Feb 2020 13:22:57 +0200 Subject: [PATCH] Task 2 - done --- ps2/ps02q/alu.v | 6 +++--- ps2/ps02q/ps02.qsf | 6 +++--- ps2/ps02q/ps02.v | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/ps2/ps02q/alu.v b/ps2/ps02q/alu.v index b51f38b..b95becf 100644 --- a/ps2/ps02q/alu.v +++ b/ps2/ps02q/alu.v @@ -23,11 +23,11 @@ //Entity declaration [part 3 of the Verilog file]. module alu #( parameter data_width = 32 -) +)( input clk, input signed [data_width - 1:0] A, input signed [data_width - 1:0] B, - input unsigned [3:0] op, + input [3:0] op, output signed [data_width - 1:0] R, output flag); @@ -62,7 +62,7 @@ always@(posedge clk) begin endcase end -assign R = reg_R(data_width - 1:0); +assign R = reg_R[data_width - 1:0]; assign flag = (reg_R[data_width]==1'b1) ? 1'b1 : 1'b0; //optional endmodule diff --git a/ps2/ps02q/ps02.qsf b/ps2/ps02q/ps02.qsf index f406ced..3fb682d 100644 --- a/ps2/ps02q/ps02.qsf +++ b/ps2/ps02q/ps02.qsf @@ -53,8 +53,8 @@ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulati # Obsolete assignment in "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top " # Obsolete assignment in "set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top " # Obsolete assignment in "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top" -set_global_assignment -name VERILOG_FILE ps02.v -set_global_assignment -name VHDL_FILE alu.vhd -set_global_assignment -name VHDL_FILE ps02_siggen.vhd set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name VERILOG_FILE alu.v +set_global_assignment -name VERILOG_FILE ps02.v +set_global_assignment -name VHDL_FILE ps02_siggen.vhd diff --git a/ps2/ps02q/ps02.v b/ps2/ps02q/ps02.v index 94db519..d5e2662 100644 --- a/ps2/ps02q/ps02.v +++ b/ps2/ps02q/ps02.v @@ -34,7 +34,7 @@ module ps02 #( parameter //define inside use signals wire signed [data_width - 1:0] A; wire signed [data_width - 1:0] B; - wire unsigned [3:0] op; + wire [3:0] op; //component declaration for A, B, op signal generator //port map for A, B, op signal generator