Task 2 - done

2020-02-16 13:22:57 +02:00
parent e2311d5b73
commit 3c38cb75a8
3 changed files with 7 additions and 7 deletions
@@ -34,7 +34,7 @@ module ps02 #( parameter
 	 //define inside use signals
 	wire signed     [data_width - 1:0]      A;
 	wire signed     [data_width - 1:0]      B;
-	wire unsigned   [3:0]                   op;
+	wire    			 [3:0]                   op;
 	
    //component declaration for A, B, op signal generator
    //port map for A, B, op signal generator