Signal sum and signal sum test bench now working.

Added overflow check logic

ld3/dds_vhdl/sin_gen.qsf

@@ -51,10 +51,11 @@ set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
 set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
 set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name VHDL_FILE sin_gen_sum.vhd
-set_global_assignment -name VHDL_FILE sin_gen_tb.vhd
-set_global_assignment -name VHDL_FILE sin_gen.vhd
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name VHDL_FILE sin_gen_sum_tb.vhd
+set_global_assignment -name VHDL_FILE sin_gen_sum.vhd
+set_global_assignment -name VHDL_FILE sin_gen_tb.vhd
+set_global_assignment -name VHDL_FILE sin_gen.vhd
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

ld3/dds_vhdl/sin_gen_sum.vhd

@@ -31,8 +31,6 @@ entity sin_gen_sum is
     (
         clk 								: in std_logic;	--100mhz clock
         rst									: in std_logic;	--rst
-        --phase_incr_one  					: in std_Logic_vector(phase_width - 1 downto 0); --"frequency for first signal"
-        --phase_incr_two  					: in std_Logic_vector(phase_width - 1 downto 0); --"frequency for second signal"
         signal_out							: out std_Logic_vector(data_width - 1 downto 0)
     );
     end sin_gen_sum;
@@ -42,7 +40,7 @@ architecture behavioral of sin_gen_sum is
     --define inside use signals
     signal signal_out_one					   : std_Logic_vector(data_width - 1 downto 0) := (others => '0');
     signal signal_out_two   					: std_Logic_vector(data_width - 1 downto 0) := (others => '0');
-	 signal signal_summ   						: std_Logic_vector(data_width downto 0) := (others => '0'); --  17bit word
+	signal signal_summ   						: signed(data_width - 1 downto 0) := (others => '0'); --  17bit word
      
     --define components to use
 	component sin_gen is
@@ -62,8 +60,9 @@ architecture behavioral of sin_gen_sum is
         end component;
 
 begin	--define the operation of the module!
-	--signal output 
+    --signal output 
-	signal_out <= std_logic_Vector(signal_summ(data_width  downto 1));
+    
+	signal_out <= std_logic_Vector(signal_summ);
 
 
 sin_gen_one : sin_gen 
@@ -99,8 +98,19 @@ port map
 	--adder
 	process(clk)
 	begin
-		if rising_edge(clk) then
+        if rising_edge(clk) then
-				signal_summ <= signed(signal_out_one) + signed(signal_out_two);
+                if ((std_logic(signal_out_one(data_width-1)) and std_logic(signal_out_two(data_width-1))) = '1' ) and
+                (signed(signal_out_one) + signed(signal_out_two) > x"0000" )
+                                             then     --max negative
+                    signal_summ <= x"8000"; --overflow
+                else if (std_logic(signal_out_one(data_width-1)) nor std_logic(signal_out_two(data_width-1))) = '1' and
+                (signed(signal_out_one) + signed(signal_out_two) < x"0000" )
+                                             then      --max positive
+                    signal_summ <= x"7fff"; --overflow
+                    else
+                    signal_summ <= signed(signal_out_one) + signed(signal_out_two);
+                    end if; 
+                end if;
 		end if;
 	end process;
 

ld3/dds_vhdl/sin_gen_sum_tb.vhd

@@ -0,0 +1,92 @@
+-----------------------------
+-- Author Imants Pulkstenis
+-- Date 09.06.2020
+-- Project name Labwork No3
+-- Module name sin_gen_sum_tb
+--
+-- Detailed module description
+-- Test bench for signal sum module
+--
+--
+-- Revision:
+-- A - initial design
+-- B - 
+--
+-----------------------------
+library ieee;					--always use this library
+use ieee.std_logic_1164.all;	--always use this library
+
+use ieee.numeric_std.all;		--use this library if arithmetic required
+
+--define connections to outside
+entity sin_gen_sum_tb is
+    generic
+    (
+        phase_width 						: integer := 9;
+        data_width							: integer := 16;
+		  phase_incr_one                      : integer := 37;
+        phase_incr_two                      : integer := 57
+    );
+    end sin_gen_sum_tb;
+
+
+--define inside of the module
+architecture behavioral of sin_gen_sum_tb is
+
+	--signals
+		--signals
+        signal clk 									: std_logic := '0';	--100mhz clock
+        signal rst									: std_logic := '0';	--rst
+        signal signal_out							: std_Logic_vector(data_width - 1 downto 0) := (others => '0');
+
+    --define components to use
+    component sin_gen_sum is
+        generic
+        (
+            phase_width 						: integer := 9;
+            data_width							: integer := 16;
+            phase_incr_one                      : integer := phase_incr_one;
+            phase_incr_two                      : integer := phase_incr_two
+        );
+        port
+        (
+            clk 								: in std_logic;	--100mhz clock
+            rst									: in std_logic;	--rst
+            signal_out							: out std_Logic_vector(data_width - 1 downto 0)--;
+            --fs_out							: in std_logic
+        );
+    end component;
+
+    constant clk_period : time := 10 ns;
+
+    begin    
+    clk <= not clk after clk_period/2;
+	
+	uut : sin_gen_sum 
+	generic map
+	(
+		phase_width 				=> phase_width,
+        	data_width				=> data_width,
+        	phase_incr_one                      	=> phase_incr_one,
+        	phase_incr_two                      	=> phase_incr_two
+	)
+	port map
+	(
+		clk 								=> clk,
+		rst								=> rst,
+		signal_out							=> signal_out
+	);
+
+    --tb process
+    process
+	begin
+	rst <= '1';
+	wait for 100 ns;
+	rst <= '0';
+	
+	wait;
+	end process;
+
+
+
+end behavioral;