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Signal sum and signal sum test bench now working.

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Added overflow check logic
This commit is contained in:
imants
2020-06-09 14:40:44 +03:00
parent 56e16842e4
commit 01e4a4b6d3
4 changed files with 114 additions and 11 deletions
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ld3/dds_vhdl/sin_gen.qsf
+4 -3
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@@ -51,10 +51,11 @@ set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VHDL_FILE sin_gen_sum.vhd
set_global_assignment -name VHDL_FILE sin_gen_tb.vhd
set_global_assignment -name VHDL_FILE sin_gen.vhd
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VHDL_FILE sin_gen_sum_tb.vhd
set_global_assignment -name VHDL_FILE sin_gen_sum.vhd
set_global_assignment -name VHDL_FILE sin_gen_tb.vhd
set_global_assignment -name VHDL_FILE sin_gen.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top