204 lines
10 KiB
Plaintext
Executable File
204 lines
10 KiB
Plaintext
Executable File
; --COPYRIGHT--,BSD_EX
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; Copyright (c) 2012, Texas Instruments Incorporated
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; All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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;
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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;
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the distribution.
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;
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; * Neither the name of Texas Instruments Incorporated nor the names of
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; its contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;
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; ******************************************************************************
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;
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; MSP430 CODE EXAMPLE DISCLAIMER
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;
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; MSP430 code examples are self-contained low-level programs that typically
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; demonstrate a single peripheral function or device feature in a highly
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; concise manner. For this the code may rely on the device's power-on default
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; register values and settings such as the clock configuration and care must
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; be taken when combining code from several examples to avoid potential side
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; effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware
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; for an API functional library-approach to peripheral configuration.
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;
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; --/COPYRIGHT--
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;******************************************************************************
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; MSP430F20xx Demo - I2C Slave Transmitter, single byte
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;
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; Description: I2C Slave communicates with I2C Master using
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; the USI. Slave data is sent and increments from 0x00 with each transmitted
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; byte which is verified by the Master.
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; LED off for address or data Ack; LED on for address or data NAck.
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; ACLK = n/a, MCLK = SMCLK = Calibrated 1MHz
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;
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; ***THIS IS THE SLAVE CODE***
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;
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; Slave Master
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; (msp430x20x3_usi_06.s43)
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; MSP430F20x2/3 MSP430F20x2/3
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; ----------------- -----------------
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; /|\| XIN|- /|\| XIN|-
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; | | | | | |
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; --|RST XOUT|- --|RST XOUT|-
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; | | | |
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; LED <-|P1.0 | | |
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; | | | P1.0|-> LED
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; | SDA/P1.7|------->|P1.7/SDA |
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; | SCL/P1.6|<-------|P1.6/SCL |
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;
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; Note: internal pull-ups are used in this example for SDA & SCL
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;
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; P. Thanigai
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; Texas Instruments Inc.
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; May 2007
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; Built with IAR Embedded Workbench Version: 3.42A
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;******************************************************************************
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#include <msp430.h>
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#define I2CState R4
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#define slav_data R5
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#define slav_add R6
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;-------------------------------------------------------------------------------
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RSEG CSTACK ; Define stack segment
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;-------------------------------------------------------------------------------
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RSEG CODE ; Assemble to Flash memory
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EVEN
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;-------------------------------------------------------------------------------
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RESET mov.w #0280h,SP ; Initialize stackpointer
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StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop watchdog timer
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CheckCal cmp.b #0xFF,&CALBC1_1MHZ ; Check calibration constants
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jne Load ; if not erased, load.
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Trap jmp Trap ; if erased do not load, trap CPU!
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Load clr.b &DCOCTL ; Select lowest DCOx and MODx settings
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mov.b &CALBC1_1MHZ,&BCSCTL1 ; Set DCO to 1MHz
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mov.b &CALDCO_1MHZ,&DCOCTL
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SetupP1 mov.b #0xC0,&P1OUT ; P1.6 & P1.7 as pullups
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bis.b #0xC0,&P1REN ; P1.6 & P1.7 as pullups
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mov.b #0xFF,&P1DIR ; unused pins output direction
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SetupP2 clr.b &P2OUT ;
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mov.b #0xFF,&P2DIR
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SetupUSI mov.b #USIPE6+USIPE7+USISWRST,&USICTL0; Port, I2C slave
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mov.b #USIIE+USII2C+USISTTIE,&USICTL1 ;Enable I2C mode,interrupts
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mov.b #USICKPL,&USICKCTL ; Setup clock polarity
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bis.b #USIIFGCC,&USICNT ; Disable automatic clear control
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bic.b #USISWRST,&USICTL0 ; Enable USI
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bic.b #USIIFG,&USICTL1 ; Clear pending flag
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clr.w I2CState
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clr.b slav_data
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mov.b #0x90,slav_add
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Mainloop
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bis.w #LPM0+GIE,SR ; Enter LPM0, enable interrupts
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jmp Mainloop
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;-------------------------------------------------------------------------------
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USI_ISR
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;-------------------------------------------------------------------------------
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bit.b #USISTTIFG,&USICTL1 ; Start entry?
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jnc Check_State
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bis.b #0x01,&P1OUT ; turn on LED, sequence start
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mov.w #2,I2CState ; First I2C state, Rx address
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Check_State add.w I2CState,PC ; I2C State Machine
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jmp STATE0
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jmp STATE2
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jmp STATE4
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jmp STATE6
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jmp STATE8
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jmp STATE10
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jmp STATE12
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STATE0 nop ; Idle, should not get here
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bic.b #USIIFG,&USICTL1
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reti
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STATE2 ; Receive slave address
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mov.b &USICNT,R8 ; Bit counter = 8, Rx address
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and.b #0xE0,R8
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add.b #0x8,R8
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mov.b R8,&USICNT
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bic.b #USISTTIFG,&USICTL1 ; Clear Start flag
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mov.w #4,I2CState ; Go to next state, chk address
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bic.b #USIIFG,&USICTL1
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reti
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STATE4 ; Process address and send (N)ack
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bit.b #0X01,&USISRL ; If read
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jnc Chk_Add
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inc.b slav_add ; Save R/W bit
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Chk_Add
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bis.b #USIOE,&USICTL0 ; SDA = output
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cmp.b slav_add,&USISRL ; address match?
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jnz Add_NACK
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clr.b &USISRL ; Send ack
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bic.b #0x01,&P1OUT ; LED off
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mov.w #8,I2CState ; Go to next state: Tx data
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bis.b #0x01,&USICNT ; Send Ack bit
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bic.b #USIIFG,&USICTL1
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reti
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Add_NACK
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mov.b #0xFF,&USISRL ; Send NACK
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bis.b #0x1,&P1OUT ; LED on:error
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mov.w #6,I2CState ; Go to next state, prep stop
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bis.b #0x01,&USICNT ; Bit counter = 1, Send Nack
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bic.b #USIIFG,&USICTL1
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reti
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STATE6 ; Prep for start condition
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bic.b #USIOE,&USICTL0 ; SDA = input
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mov.b #0x90,slav_add ; Reset Slave address
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clr.w I2CState ; Reset state machine
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bic.b #USIIFG,&USICTL1
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reti
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STATE8 ; Send data byte
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bis.b #USIOE,&USICTL0 ; SDA =output
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mov.b slav_data,&USISRL ; send data byte
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bis.b #0x8,&USICNT ; Bit counter = 8
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mov.w #10,I2CState ; Go to next state, generate stop
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bic.b #USIIFG,&USICTL1
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reti
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STATE10 ; Receive Data (N)Ack
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bic.b #USIOE,&USICTL0 ; SDA = input
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bis.b #0x01,&USICNT ; Receive (N)ack
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mov.w #12,I2CState ; Go to next state: check (N)ack
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bic.b #USIIFG,&USICTL1
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reti
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STATE12
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bit.b #0x01,&USISRL ; If Nack received
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jnc Data_Rx
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bis.b #0x01,&P1OUT ; Led ON :error
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bic.b #USIOE,&USICTL0 ; SDA = input
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jmp STATE12_Exit
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Data_Rx
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bic.b #0x01,&P1OUT ; LED off
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inc.b slav_data ; Increment slave data
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bic.b #USIOE,&USICTL0 ; SDA = input
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STATE12_Exit
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mov.b #0x90,slav_add ; Reset slave address
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clr.w I2CState ; Reset state machine
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bic.b #USIIFG,&USICTL1
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reti
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;-------------------------------------------------------------------------------
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; Interrupt Vectors Used MSP430x2013
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;-------------------------------------------------------------------------------
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COMMON INTVEC
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ORG RESET_VECTOR ; MSP430 RESET Vector
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DW RESET ;
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ORG USI_VECTOR ; USICNT
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DW USI_ISR ;
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END
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