129 lines
6.7 KiB
Plaintext
Executable File
129 lines
6.7 KiB
Plaintext
Executable File
; --COPYRIGHT--,BSD_EX
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; Copyright (c) 2012, Texas Instruments Incorporated
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; All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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;
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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;
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the distribution.
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;
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; * Neither the name of Texas Instruments Incorporated nor the names of
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; its contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;
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; ******************************************************************************
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;
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; MSP430 CODE EXAMPLE DISCLAIMER
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;
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; MSP430 code examples are self-contained low-level programs that typically
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; demonstrate a single peripheral function or device feature in a highly
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; concise manner. For this the code may rely on the device's power-on default
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; register values and settings such as the clock configuration and care must
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; be taken when combining code from several examples to avoid potential side
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; effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware
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; for an API functional library-approach to peripheral configuration.
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;
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; --/COPYRIGHT--
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;*******************************************************************************
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; MSP430F20x2 Demo - ADC10, Sample A7, 1.5V, TA1 Trig, Ultra-Low Pwr
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;
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; Description: A7 is sampled 1024/second (32xACLK) with reference to 1.5V.
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; All activity is interrupt driven with proper usage of MSP430 low-power
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; modes, ADC10 and Vref demonstrated. Timer_A with both TA1/TA0 used in
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; upmode to drive ADC10 conversion (continuous mode can also be used).
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; Inside of TA0_ISR software will enable ADC10 and internal reference and
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; allow > 30us delay for Vref to stabilize prior to sample start. Sample
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; start is automatically triggered by TA1 every 32 ACLK cycles. ADC10_ISR
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; will disable ADC10 and Vref and compare ADC10 conversion code. Internal
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; oscillator times sample (16x) and conversion (13x). If A7 > 0.2Vcc,
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; P1.0 is set, else reset. Normal Mode is LPM3.
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; //* An external watch crystal on XIN XOUT is required for ACLK *//
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;
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; +-----(0.9766us)---------\\------------------>+
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; TA0_ISR TA1 ADC10_ISR TA0_ISR TA1
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; -----+------------+------------+-----------\\------+------------+----->
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; Enable ADC Trigger ADC Disable ADC
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; and Vref Compare
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; +-( >30us--->+
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;
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;
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; MSP430F20x2
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; -----------------
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; /|\| XIN|-
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; | | | 32kHz
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; --|RST XOUT|-
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; | |
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; >---|P1.7/A7 P1.0 |--> LED
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;
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; L. Westlund
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; Texas Instruments Inc.
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; May 2006
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; Built with IAR Embedded Workbench Version: 3.41A
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;*******************************************************************************
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#include <msp430.h>
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;-------------------------------------------------------------------------------
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RSEG CSTACK ; Define stack segment
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;-------------------------------------------------------------------------------
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RSEG CODE ; Assemble to Flash memory
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;-------------------------------------------------------------------------------
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RESET mov.w #SFE(CSTACK),SP ; Initialize stackpointer
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StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop WDT
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SetupADC10 mov.w #INCH_7+SHS_1,&ADC10CTL1 ; P1.7, TA1 trigger sample start
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bis.b #080h,&ADC10AE0 ; P1.7 ADC10 option select
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SetupP1 bis.b #001h,&P1DIR ; P1.0 output
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SetupC0 mov.w #CCIE,&TACCTL0 ; Enable interrupt
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mov.w #32-1,&TACCR0 ; PWM Period
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SetupC1 mov.w #OUTMOD_3,&TACCTL1 ; TACCR1 set/reset
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mov.w #2,&TACCR1 ; TACCR1 PWM Duty Cycle
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SetupTA mov.w #TASSEL_1+MC_1,TACTL ; ACLK, up mode
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;
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Mainloop bis.w #LPM3+GIE,SR ; Enter LPM3
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nop ; Required only for debugger
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;
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;-------------------------------------------------------------------------------
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ADC10_ISR;
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;-------------------------------------------------------------------------------
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bic.w #ENC,&ADC10CTL0 ; ADC10 disabled
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clr.w &ADC10CTL0 ; ADC10, Vref disabled completely
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bic.b #01h,&P1OUT ; P1.0 = 0
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cmp.w #088h,&ADC10MEM ; ADC10MEM = A7 > 0.2V?
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jlo ADC10_Exit ; Again
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bis.b #01h,&P1OUT ; P1.0 = 1
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ADC10_Exit reti ;
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;
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;-------------------------------------------------------------------------------
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TA0_ISR; ISR for TACCR0
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;-------------------------------------------------------------------------------
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mov.w #SREF_1+ADC10SHT_2+REFON+ADC10ON+ADC10IE,&ADC10CTL0;
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bis.w #ENC,&ADC10CTL0 ; ADC10 enable set
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reti ;
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;
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;-------------------------------------------------------------------------------
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COMMON INTVEC ; Interrupt Vectors
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;-------------------------------------------------------------------------------
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ORG ADC10_VECTOR ; ADC10 Vector
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DW ADC10_ISR
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ORG TIMERA0_VECTOR ; Timer_A0 Vector
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DW TA0_ISR
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ORG RESET_VECTOR ; POR, ext. Reset
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DW RESET
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END
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