121 lines
6.4 KiB
Plaintext
Executable File
121 lines
6.4 KiB
Plaintext
Executable File
; --COPYRIGHT--,BSD_EX
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; Copyright (c) 2012, Texas Instruments Incorporated
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; All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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;
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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;
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the distribution.
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;
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; * Neither the name of Texas Instruments Incorporated nor the names of
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; its contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;
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; ******************************************************************************
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;
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; MSP430 CODE EXAMPLE DISCLAIMER
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;
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; MSP430 code examples are self-contained low-level programs that typically
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; demonstrate a single peripheral function or device feature in a highly
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; concise manner. For this the code may rely on the device's power-on default
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; register values and settings such as the clock configuration and care must
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; be taken when combining code from several examples to avoid potential side
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; effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware
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; for an API functional library-approach to peripheral configuration.
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;
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; --/COPYRIGHT--
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;*******************************************************************************
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; MSP430F20x2 Demo - ADC10, DTC Sample A1 32x, 1.5V, Repeat Single, DCO
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;
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; Description: Use DTC to sample A1 32 times with reference to internal 1.5v.
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; Vref Software writes to ADC10SC to trigger sample burst. In Mainloop MSP430
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; waits in LPM0 to save power until ADC10 conversion complete, ADC10_ISR(DTC)
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; will force exit from any LPMx in Mainloop on reti. ADC10 internal
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; oscillator times sample period (16x) and conversion (13x). DTC transfers
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; conversion code to RAM 200h - 240h. P1.0 set at start of conversion burst,
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; reset on completion.
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;
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; MSP430F20x2
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; -----------------
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; /|\| XIN|-
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; | | |
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; --|RST XOUT|-
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; | |
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; >---|P1.1/A1 P1.0|-->LED
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;
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; L. Westlund
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; Texas Instruments Inc.
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; May 2006
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; Built with IAR Embedded Workbench Version: 3.41A
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;*******************************************************************************
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#include <msp430.h>
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;-------------------------------------------------------------------------------
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RSEG CSTACK ; Define stack segment
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;-------------------------------------------------------------------------------
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RSEG CODE ; Assemble to Flash memory
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;-------------------------------------------------------------------------------
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RESET mov.w #SFE(CSTACK),SP ; Initialize stackpointer
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StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop WDT
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SetupADC10 mov.w #CONSEQ_2+INCH_1,&ADC10CTL1 ; Repeat single channel
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mov.w #SREF_1+ADC10SHT_2+MSC+REFON+ADC10ON+ADC10IE,&ADC10CTL0;
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mov.w #30,&TACCR0 ; Delay to allow Ref to settle
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bis.w #CCIE,&TACCTL0 ; Compare-mode interrupt.
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mov.w #TACLR+MC_1+TASSEL_2,&TACTL; up mode, SMCLK
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bis.w #LPM0+GIE,SR ; Enter LPM0, enable interrupts
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bic.w #CCIE,&TACCTL0 ; Disable timer interrupt
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dint ; Disable Interrupts
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mov.b #020h,&ADC10DTC1 ; 32 conversions
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bis.b #02h,&ADC10AE0 ; P1.1 ADC option select
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SetupP1 bis.b #001h,&P1DIR ; P1.0 output
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;
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Mainloop bic.w #ENC,&ADC10CTL0 ;
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busy_test bit #BUSY,&ADC10CTL1 ; ADC10 core inactive?
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jnz busy_test ;
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mov.w #0200h,&ADC10SA ; Data buffer start
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bis.b #001h,&P1OUT ; P1.0 = 1
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bis.w #ENC+ADC10SC,&ADC10CTL0 ; Start sampling
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bis.w #CPUOFF+GIE,SR ; LPM0, ADC10_ISR will force exit
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bic.b #001h,&P1OUT ; P1.0 = 0
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jmp Mainloop ; Again
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;
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;-------------------------------------------------------------------------------
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TA0_ISR; ISR for TACCR0
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;-------------------------------------------------------------------------------
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clr.w &TACTL ; Clear Timer_A control registers
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bic.w #LPM0,0(SP) ; Exit LPM0 on reti
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reti ;
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;-------------------------------------------------------------------------------
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ADC10_ISR; Exit LPM0 on reti
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;-------------------------------------------------------------------------------
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bic.w #CPUOFF,0(SP) ; Exit LPM0 on reti
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reti ;
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;
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;-------------------------------------------------------------------------------
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COMMON INTVEC ; Interrupt Vectors
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;-------------------------------------------------------------------------------
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ORG ADC10_VECTOR ; ADC10 Vector
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DW ADC10_ISR
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ORG TIMERA0_VECTOR ; Timer_A0 Vector
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DW TA0_ISR
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ORG RESET_VECTOR ; POR, ext. Reset
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DW RESET
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END
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