106 lines
5.4 KiB
Plaintext
Executable File
106 lines
5.4 KiB
Plaintext
Executable File
; --COPYRIGHT--,BSD_EX
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; Copyright (c) 2012, Texas Instruments Incorporated
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; All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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;
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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;
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the distribution.
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;
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; * Neither the name of Texas Instruments Incorporated nor the names of
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; its contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;
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; ******************************************************************************
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;
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; MSP430 CODE EXAMPLE DISCLAIMER
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;
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; MSP430 code examples are self-contained low-level programs that typically
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; demonstrate a single peripheral function or device feature in a highly
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; concise manner. For this the code may rely on the device's power-on default
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; register values and settings such as the clock configuration and care must
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; be taken when combining code from several examples to avoid potential side
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; effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware
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; for an API functional library-approach to peripheral configuration.
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;
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; --/COPYRIGHT--
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;*******************************************************************************
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; MSP430F20xx Demo - Timer_A, Toggle P1.0, CCR1 Cont. Mode ISR, DCO SMCLK
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;
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; Description: Toggle P1.0 using software and TA_1 ISR. Toggles every
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; 50000 SMCLK cycles. SMCLK provides clock source for TACLK.
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; During the TA_1 ISR, P1.0 is toggled and 50000 clock cycles are added to
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; CCR0. TA_1 ISR is triggered every 50000 cycles. CPU is normally off and
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; used only during TA_ISR. Proper use of the TAIV interrupt vector
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; generator is demonstrated.
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; ACLK = n/a, MCLK = SMCLK = TACLK = default DCO
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;
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; MSP430F20xx
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; -----------------
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; /|\| XIN|-
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; | | |
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; --|RST XOUT|-
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; | |
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; | P1.0|-->LED
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;
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; M. Buccini / L. Westlund
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; Texas Instruments Inc.
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; September 2005
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; Built with IAR Embedded Workbench Version: 3.40A
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;*******************************************************************************
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#include <msp430.h>
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;-------------------------------------------------------------------------------
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ORG 0F800h ; Program Reset
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;-------------------------------------------------------------------------------
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RESET mov.w #0280h,SP ; Initialize stackpointer
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StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop WDT
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SetupP1 bis.b #001h,&P1DIR ; P1.0 output
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SetupC1 mov.w #CCIE,&CCTL1 ; CCR1 interrupt enabled
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mov.w #50000,&CCR1 ;
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SetupTA mov.w #TASSEL_2+MC_2,&TACTL ; SMCLK, contmode
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;
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Mainloop bis.w #CPUOFF+GIE,SR ; CPU off, interrupts enabled
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nop ; Required only for debugger
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;
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;-------------------------------------------------------------------------------
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TAX_ISR; Common ISR for CCR1-4 and overflow
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;-------------------------------------------------------------------------------
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add.w &TAIV,PC ; Add Timer_A offset vector
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reti ; CCR0 - no source
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jmp CCR1_ISR ; CCR1
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reti ; CCR2
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reti ; CCR3
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reti ; CCR4
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TA_over reti ; Return from overflow ISR
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;
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CCR1_ISR add.w #50000,&CCR1 ; Offset until next interrupt
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xor.b #001h,&P1OUT ; Toggle P1.0
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reti ; Return from overflow ISR
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;
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;-------------------------------------------------------------------------------
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; Interrupt Vectors
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;-------------------------------------------------------------------------------
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ORG 0FFFEh ; MSP430 RESET Vector
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DW RESET ;
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ORG 0FFF0h ; Timer_AX Vector
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DW TAX_ISR ;
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END
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