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+/* --COPYRIGHT--,BSD_EX
+ * Copyright (c) 2012, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************
+ * 
+ *                       MSP430 CODE EXAMPLE DISCLAIMER
+ *
+ * MSP430 code examples are self-contained low-level programs that typically
+ * demonstrate a single peripheral function or device feature in a highly
+ * concise manner. For this the code may rely on the device's power-on default
+ * register values and settings such as the clock configuration and care must
+ * be taken when combining code from several examples to avoid potential side
+ * effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware
+ * for an API functional library-approach to peripheral configuration.
+ *
+ * --/COPYRIGHT--*/
+//******************************************************************************
+//  MSP430F20xx Demo - LFXT1 Oscillator Fault Detection
+//
+//  Description: System runs normally in LPM3 with WDT timer clocked by
+//  32kHz ACLK with a 1x4 second interrupt. P1.0 is normally pulsed every
+//  second inside WDT interrupt. If an LFXT1 oscillator fault occurs,
+//  NMI is requested forcing exit from LPM3. P1.0 is toggled rapidly by software
+//  as long as LFXT1 oscillator fault is present. Assumed only LFXT1 as NMI
+//  source - code does not check for other NMI sources.
+//  ACLK = LFXT1 = 32768, MCLK = SMCLK = Default DCO
+//
+//  //*External watch crystal on XIN XOUT is required for ACLK*//	
+//
+//
+//           MSP430F20xx
+//         ---------------
+//     /|\|            XIN|-
+//      | |               | 32kHz
+//      --|RST        XOUT|-
+//        |               |
+//        |           P1.0|-->LED
+//
+//  M. Buccini / L. Westlund
+//  Texas Instruments Inc.
+//  September 2005
+//  Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: 3.40A
+//******************************************************************************
+
+#include <msp430.h>
+volatile unsigned int i;
+
+int main(void)
+{
+  WDTCTL = WDT_ADLY_1000;                   // WDT 1s interval timer
+  IE1 |= WDTIE;                             // Enable WDT interrupt
+  P1DIR = 0xFF;                             // All P1.x outputs
+  P1OUT = 0;                                // All P1.x reset
+  P2DIR = 0xFF;                             // All P2.x outputs
+  P2OUT = 0;                                // All P2.x reset
+// An immedate Osc Fault will occur next
+  IE1 |= OFIE;                              // Enable Osc Fault
+
+  while(1)
+  {
+   P1OUT ^= 0x01;                           // Toggle P1.0 using exclusive-OR
+  __bis_SR_register(LPM3_bits + GIE);       // Enter LPM3 w/interrupt
+  }
+}
+
+#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
+#pragma vector=WDT_VECTOR
+__interrupt void watchdog_timer (void)
+#elif defined(__GNUC__)
+void __attribute__ ((interrupt(WDT_VECTOR))) watchdog_timer (void)
+#else
+#error Compiler not supported!
+#endif
+{
+    __bic_SR_register_on_exit(LPM3_bits);   // Clear LPM3 bits from 0(SR)
+}
+
+#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
+#pragma vector=NMI_VECTOR
+__interrupt void nmi_ (void)
+#elif defined(__GNUC__)
+void __attribute__ ((interrupt(NMI_VECTOR))) nmi_ (void)
+#else
+#error Compiler not supported!
+#endif
+{
+  do
+  {
+    IFG1 &= ~OFIFG;                         // Clear OSCFault flag
+    for (i = 0xFFF; i > 0; i--);            // Time for flag to set
+    P1OUT ^= 0x01;                          // Toggle P1.0 using exclusive-OR
+  }
+  while (IFG1 & OFIFG);                     // OSCFault flag still set?
+  IE1 |= OFIE;                              // Enable Osc Fault
+}