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Imants Pulkstenis
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; --COPYRIGHT--,BSD_EX
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; Copyright (c) 2012, Texas Instruments Incorporated
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; All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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;
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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;
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the distribution.
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;
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; * Neither the name of Texas Instruments Incorporated nor the names of
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; its contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;
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; ******************************************************************************
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;
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; MSP430 CODE EXAMPLE DISCLAIMER
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;
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; MSP430 code examples are self-contained low-level programs that typically
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; demonstrate a single peripheral function or device feature in a highly
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; concise manner. For this the code may rely on the device's power-on default
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; register values and settings such as the clock configuration and care must
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; be taken when combining code from several examples to avoid potential side
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; effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware
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; for an API functional library-approach to peripheral configuration.
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;
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; --/COPYRIGHT--
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;******************************************************************************
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; MSP430F20x2/3 Demo - SPI full-Duplex 3-wire Master
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;
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; Description: SPI Master communicates full-duplex with SPI Slave using
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; 3-wire mode. The level on P1.4 is TX'ed and RX'ed to P1.0.
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; Master will pulse slave P1.2 which resets USICNT counter for synch start.
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; ACLK = n/a, MCLK = SMCLK = Default DCO
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;
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; Slave Master
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; MSP430F20x2/3 MSP430F20x2/3
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; ----------------- -----------------
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; | XIN|- /|\| XIN|-
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; | | | | |
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; | XOUT|- --|RST XOUT|-
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; | | /|\ | |
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; | RST/NMI|--+<----|P1.2 |
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; LED <-|P1.0 | | P1.4|<-
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; ->|P1.4 | | P1.0|-> LED
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; | SDI/P1.7|<-------|P1.6/SDO |
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; | SDO/P1.6|------->|P1.7/SDI |
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; | SCLK/P1.5|<-------|P1.5/SCLK |
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;
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; M. Buccini
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; Texas Instruments, Inc
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; October 2005
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;******************************************************************************
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#include <msp430.h>
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;-----------------------------------------------------------------------------
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ORG 0F800h ; Program Reset
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;-----------------------------------------------------------------------------
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RESET mov.w #0280h,SP ; Initialize stackpointer
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StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop watchdog timer
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SetupP1 mov.b #010h,&P1OUT ; P1.4 set, else
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bis.b #010h,&P1REN ; P1.4 pullup
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bis.b #001h,&P1DIR ;
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SetupUSI bis.b #USIPE7+USIPE6+USIPE5+USIMST+USIOE,&USICTL0; Port, SPI master
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bis.b #USIIE,&USICTL1 ; Counter interrupt, flag remains
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mov.b #USIDIV_4+USISSEL_2,&USICKCTL ; /16 SMCLK
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bic.b #USISWRST,&USICTL0 ; Enable USI
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mov.b &P1IN,&USISRL ; init-load TX data
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ResetSlave bis.b #004h,&P1DIR ; Reset Slave
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bic.b #004h,&P1DIR ;
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clr.w R4 ; Delay for Slave
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Delay dec.w R4 ;
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jnz Delay ;
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mov.b #08h,&USICNT ; init-load counter, clear flag
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;
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Mainloop bis.b #LPM0+GIE,SR ; CPU off w/ interrupts enabled
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nop ; Required for debugger only
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;
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;------------------------------------------------------------------------------
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USI_ISR;
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;------------------------------------------------------------------------------
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mov.b &USISRL,R4 ; Temp save RX'ed char
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mov.b &P1IN,&USISRL ;
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bic.b #01h,&P1OUT ;
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bit.b #010h,R4 ;
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jnc L2 ;
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L1 bis.b #01h,&P1OUT ;
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L2 mov.b #08h,&USICNT ; re-load counter, clear flag
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reti ; Exit ISR
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;
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;------------------------------------------------------------------------------
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; Interrupt Vectors Used MSP430x20x2/3
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;------------------------------------------------------------------------------
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ORG 0FFFEh ; MSP430 RESET Vector
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DW RESET ;
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ORG 0FFE8h ; USICNT
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DW USI_ISR ;
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END
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