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Imants Pulkstenis
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; --COPYRIGHT--,BSD_EX
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; Copyright (c) 2012, Texas Instruments Incorporated
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; All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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;
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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;
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the distribution.
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;
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; * Neither the name of Texas Instruments Incorporated nor the names of
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; its contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;
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; ******************************************************************************
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;
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; MSP430 CODE EXAMPLE DISCLAIMER
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;
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; MSP430 code examples are self-contained low-level programs that typically
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; demonstrate a single peripheral function or device feature in a highly
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; concise manner. For this the code may rely on the device's power-on default
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; register values and settings such as the clock configuration and care must
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; be taken when combining code from several examples to avoid potential side
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; effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware
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; for an API functional library-approach to peripheral configuration.
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;
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; --/COPYRIGHT--
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;*******************************************************************************
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; MSP430F20xx Demo - Timer_A, Ultra-Low Pwr UART 2400 Echo, 32kHz ACLK
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;
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; Description: Use Timer_A CCR0 hardware output modes and SCCI data latch
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; to implement UART function @ 2400 baud. Software does not directly read and
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; write to RX and TX pins, instead proper use of output modes and SCCI data
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; latch are demonstrated. Use of these hardware features eliminates ISR
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; latency effects as hardware insures that output and input bit latching and
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; timing are perfectly synchronised with Timer_A regardless of other
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; software activity. In the Mainloop the UART function readies the UART to
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; receive one character and waits in LPM3 with all activity interrupt driven.
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; After a character has been received, the UART receive function forces exit
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; from LPM3 in the Mainloop which echo's back the received character.
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; ACLK = TACLK = LFXT1 = 32768Hz, MCLK = SMCLK = default DCO
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; //* An external watch crystal is required on XIN XOUT for ACLK *//
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;
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; MSP430F20xx
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; -----------------
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; /|\| XIN|-
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; | | | 32kHz
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; --|RST XOUT|-
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; | |
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; | CCI0B/TXD/P1.5|-------->
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; | | 2400 8N1
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; | CCI0A/RXD/P1.1|<--------
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;
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;
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; M. Buccini / L. Westlund
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; Texas Instruments Inc.
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; October 2005
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; Built with IAR Embedded Workbench Version: 3.40A
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;*******************************************************************************
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RXD EQU 002h ; RXD on P1.1
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TXD EQU 020h ; TXD on P1.5
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;
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; CPU Registers Used
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#define RXTXData R4
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#define BitCnt R5
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;
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; Conditions for 2400 Baud SW UART, ACLK = 32768
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Bitime_5 EQU 06 ; ~0.5 bit length + small adjustment
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Bitime EQU 014 ; 427us bit length ~ 2341 baud
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#include <msp430.h>
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;-------------------------------------------------------------------------------
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ORG 0F800h ; Program Reset
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;-------------------------------------------------------------------------------
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RESET mov.w #0280h,SP ; Initialize stackpointer
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StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop Watchdog Timer
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SetupTA mov.w #TASSEL_1+MC_2,&TACTL ; ACLK, continuous mode
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SetupC0 mov.w #OUT,&CCTL0 ; TXD Idle as Mark
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SetupP1 bis.b #TXD+RXD,&P1SEL ;
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bis.b #TXD,&P1DIR ;
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;
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Mainloop call #RX_Ready ; UART ready to RX one Byte
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bis.w #LPM3+GIE,SR ; Enter LPM3 w/ int until Byte RXed
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call #TX_Byte ; TX Back RXed Byte Received
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jmp Mainloop ;
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;
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;-------------------------------------------------------------------------------
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TX_Byte ; Subroutine Transmits Character from RXTXData Buffer
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;-------------------------------------------------------------------------------
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TX_1 mov.w &TAR,&CCR0 ; Current state of TA counter
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cmp.w &TAR,&CCR0 ; !!Prevent async capature!!
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jne TX_1 ;
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add.w #Bitime,&CCR0 ; Some time till first bit
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bis.w #0100h, RXTXData ; Add mark stop bit to RXTXData
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rla.w RXTXData ; Add space start bit
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mov.w #10,BitCnt ; Load Bit counter, 8data + ST/SP
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mov.w #CCIS0+OUTMOD0+CCIE,&CCTL0 ; TXD = mark = idle
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TX_Wait bit.w #CCIE,&CCTL0 ; Wait for TX completion
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jnz TX_Wait ;
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ret ;
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;
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;-------------------------------------------------------------------------------
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RX_Ready ; Subroutine Readies UART to Receive Character into RXTXData Buffer
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;-------------------------------------------------------------------------------
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mov.w #08,BitCnt ; Load Bit Counter, 8 data bits
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SetupRX mov.w #CM1+SCS+OUTMOD0+CAP+CCIE,&CCTL0 ; Neg Edge,Sync,cap
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ret ;
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;
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;-------------------------------------------------------------------------------
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TA0_ISR ; RXTXData Buffer holds UART Data
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;-------------------------------------------------------------------------------
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add.w #Bitime,&CCR0 ; Time to next bit
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bit.w #CCIS0,&CCTL0 ; RX on CCI0B?
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jnz UART_TX ; Jump --> TX
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UART_RX bit.w #CAP,&CCTL0 ; Capture mode = start bit edge
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jz RX_Bit ; Start bit edge?
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RX_Edge bic.w #CAP,&CCTL0 ; Switch to compare mode
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add.w #Bitime_5,&CCR0 ; First databit 1.5 bits from edge
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reti ;
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RX_Bit bit.w #SCCI,&CCTL0 ; Get bit waiting in receive latch
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rrc.b RXTXData ; Store received bit
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RX_Test dec.w BitCnt ; All bits RXed?
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jnz RX_Next ; Next bit?
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;>>>>>>>>>> Decode of Received Byte Here <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
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RX_Comp bic.w #CCIE,&CCTL0 ; All bits RXed, disable interrupt
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mov.w #GIE,0(SP) ; Decode byte = active in Mainloop
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;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
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RX_Next reti ;
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;
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UART_TX cmp.w #00h,BitCnt ;
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jne TX_Next ; Next bit?
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bic.w #CCIE,&CCTL0 ; All Bits TX or RX, Disable Int.
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reti ;
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TX_Next bic.w #OUTMOD2,&CCTL0 ; TX Mark
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rra.w RXTXData ; LSB is shifted to carry
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jc TX_Test ; Jump --> bit = 1
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TX_Space bis.w #OUTMOD2,&CCTL0 ; TX Space
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TX_Test dec.w BitCnt ; All bits sent (or received)?
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reti ;
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;
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;-------------------------------------------------------------------------------
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; Interrupt Vectors
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;-------------------------------------------------------------------------------
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ORG 0FFFEh ; MSP430 RESET Vector
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DW RESET ;
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ORG 0FFF2h ; Timer_A0 Vector
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DW TA0_ISR ;
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END
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