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Imants Pulkstenis
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; --COPYRIGHT--,BSD_EX
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; Copyright (c) 2012, Texas Instruments Incorporated
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; All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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;
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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;
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the distribution.
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;
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; * Neither the name of Texas Instruments Incorporated nor the names of
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; its contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;
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; ******************************************************************************
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;
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; MSP430 CODE EXAMPLE DISCLAIMER
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;
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; MSP430 code examples are self-contained low-level programs that typically
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; demonstrate a single peripheral function or device feature in a highly
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; concise manner. For this the code may rely on the device's power-on default
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; register values and settings such as the clock configuration and care must
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; be taken when combining code from several examples to avoid potential side
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; effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware
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; for an API functional library-approach to peripheral configuration.
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;
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; --/COPYRIGHT--
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;*******************************************************************************
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; MSP430F20xx Demo - LFXT1 Oscillator Fault Detection
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;
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; Description: System runs normally in LPM3 with WDT timer clocked by
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; 32kHz ACLK with a 1x4 second interrupt. P1.0 is normally pulsed every
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; second inside WDT interrupt. If an LFXT1 oscillator fault occurs,
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; NMI is requested forcing exit from LPM3. P1.0 is toggled rapidly by software
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; as long as LFXT1 oscillator fault is present. Assumed only LFXT1 as NMI
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; source - code does not check for other NMI sources.
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; ACLK = LFXT1 = 32768, MCLK = SMCLK = Default DCO
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;
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; //*External watch crystal on XIN XOUT is required for ACLK*//
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;
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;
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; MSP430F20xx
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; ---------------
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; /|\| XIN|-
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; | | | 32kHz
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; --|RST XOUT|-
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; | |
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; | P1.0|-->LED;
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;
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; M. Buccini / L. Westlund
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; Texas Instruments Inc.
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; October 2005
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; Built with IAR Embedded Workbench Version: 3.40A
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;*******************************************************************************
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#include <msp430.h>
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;-------------------------------------------------------------------------------
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ORG 0F800h ; Program Reset
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;-------------------------------------------------------------------------------
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RESET mov.w #0280h,SP ; Initialize stackpointer
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StopWDT mov.w #WDT_ADLY_1000,&WDTCTL ; WDT 1s interval timer
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bis.b #WDTIE,&IE1 ; Enable WDT interrupt
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SetupP1 mov.b #0FFh,&P1DIR ; All P1.x outputs
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clr.b &P1OUT ; All P1.x reset
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SetupP2 mov.b #0FFh,&P2DIR ; All P2.x outputs
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clr.b &P2OUT ; All P2.x reset
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; An immedate Osc Fault will occur next
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bis.b #OFIE,&IE1 ; Enable osc fault interrupt
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;
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Mainloop xor.b #001h,&P1OUT ; Toggle P1.0
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bis.w #LPM3+GIE,SR ; Enter LPM3, enable interrupts
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jmp Mainloop ;
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;
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;-------------------------------------------------------------------------------
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NMI_ISR; Only osc fault enabled, R15 used temporarily and not saved
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; Assumed LFXT1 is only source for NMI interrupt
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;-------------------------------------------------------------------------------
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CheckOsc bic.b #OFIFG,&IFG1 ; Clear OSC fault flag
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xor.b #001h,&P1OUT ; Toggle P1.0
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mov.w #03FFFh,R15 ; R15 = Delay
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CheckOsc1 dec.w R15 ; Time for flag to set
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jnz CheckOsc1 ;
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bit.b #OFIFG,&IFG1 ; OSC fault flag set?
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jnz CheckOsc ; OSC Fault, clear flag again
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bis.b #OFIE,&IE1 ; re-enable osc fault interrupt
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reti ; return from interrupt
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;
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;-------------------------------------------------------------------------------
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WDT_ISR; Exit LPM3 on reti
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;-------------------------------------------------------------------------------
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bic.w #LPM3,0(SP) ;
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reti ;
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;
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;-------------------------------------------------------------------------------
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; Interrupt Vectors
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;-------------------------------------------------------------------------------
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ORG 0FFF4h ; WDT Vector
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DW WDT_ISR ;
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ORG 0FFFCh ; NMI vector
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DW NMI_ISR ;
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ORG 0FFFEh ; MSP430 RESET Vector
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DW RESET ;
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END
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