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Imants Pulkstenis
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; --COPYRIGHT--,BSD_EX
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; Copyright (c) 2012, Texas Instruments Incorporated
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; All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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;
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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;
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the distribution.
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;
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; * Neither the name of Texas Instruments Incorporated nor the names of
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; its contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;
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; ******************************************************************************
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;
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; MSP430 CODE EXAMPLE DISCLAIMER
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;
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; MSP430 code examples are self-contained low-level programs that typically
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; demonstrate a single peripheral function or device feature in a highly
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; concise manner. For this the code may rely on the device's power-on default
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; register values and settings such as the clock configuration and care must
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; be taken when combining code from several examples to avoid potential side
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; effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware
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; for an API functional library-approach to peripheral configuration.
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;
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; --/COPYRIGHT--
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;*******************************************************************************
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; MSP430F20x2 Demo - ADC10, DTC Sample A1 32x, AVcc, TA0 Trig, DCO
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;
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; Description: A1 is sampled in 32x burst using DTC ever 16/second
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; (ACLK/2048) with reference to AVcc. All. Activity is interrupt driven.
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; Timer_A in upmode uses TA0 toggle to drive ADC10 conversion. Sample burst
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; is automatically triggered by TA0 rising edge every 16 ACLK cycles.
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; ADC10_ISR will exit from LPM3 mode and return CPU active. Internal ADC10OSC
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; times sample (16x) and conversion (13x). DTC transfers conversion code to
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; RAM 200h - 240h. In the Mainloop P1.0 is toggled. Normal Mode is LPM3.
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; //* An external watch crystal on XIN XOUT is required for ACLK *//
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;
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; MSP430F20x2
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; -----------------
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; /|\| XIN|-
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; | | | 32kHz
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; --|RST XOUT|-
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; | |
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; >---|P1.1/A1 P1.0 |--> LED
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;
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; L. Westlund
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; Texas Instruments Inc.
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; May 2006
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; Built with IAR Embedded Workbench Version: 3.41A
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;*******************************************************************************
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#include <msp430.h>
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;-------------------------------------------------------------------------------
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RSEG CSTACK ; Define stack segment
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;-------------------------------------------------------------------------------
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RSEG CODE ; Assemble to Flash memory
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;-------------------------------------------------------------------------------
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RESET mov.w #SFE(CSTACK),SP ; Initialize stackpointer
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StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop WDT
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SetupADC10 mov.w #INCH_1+SHS_2+CONSEQ_2,&ADC10CTL1 ; TA0 trigger
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mov.w #ADC10SHT_2+MSC+ADC10ON+ADC10IE,&ADC10CTL0;
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mov.b #020h,&ADC10DTC1 ; 32 conversions
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SetupP1 bis.b #001h,&P1DIR ; P1.0 output
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bis.b #002h,&ADC10AE0 ; P1.1 ADC10 option select
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mov.w #1024-1,&TACCR0 ; PWM Period
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SetupC0 mov.w #OUTMOD_4,&TACCTL0 ; TACCR0 toggle
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SetupTA mov.w #TASSEL_1+MC_1,TACTL ; ACLK, up mode
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;
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Mainloop bic.w #ENC,&ADC10CTL0 ;
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busy_test bit #BUSY,&ADC10CTL1 ; ADC10 core inactive?
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jnz busy_test ;
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mov.w #0200h,&ADC10SA ; Data buffer start
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bis.w #ENC,&ADC10CTL0 ; Sampling and conversion ready
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bis.w #LPM3+GIE,SR ; LPM3, ADC10_ISR will force exit
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xor.b #001h,&P1OUT ; P1.0 = toggle
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jmp Mainloop ; Again
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;
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;-------------------------------------------------------------------------------
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ADC10_ISR; Exit LPM3 on reti
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;-------------------------------------------------------------------------------
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bic.w #LPM3,0(SP) ; Exit LPM3 on reti
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reti ;
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;
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;-------------------------------------------------------------------------------
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COMMON INTVEC ; Interrupt Vectors
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;-------------------------------------------------------------------------------
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ORG ADC10_VECTOR ; ADC10 Vector
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DW ADC10_ISR
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ORG RESET_VECTOR ; POR, ext. Reset
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DW RESET
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END
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