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+; --COPYRIGHT--,BSD_EX
+;  Copyright (c) 2012, Texas Instruments Incorporated
+;  All rights reserved.
+; 
+;  Redistribution and use in source and binary forms, with or without
+;  modification, are permitted provided that the following conditions
+;  are met:
+; 
+;  *  Redistributions of source code must retain the above copyright
+;     notice, this list of conditions and the following disclaimer.
+; 
+;  *  Redistributions in binary form must reproduce the above copyright
+;     notice, this list of conditions and the following disclaimer in the
+;     documentation and/or other materials provided with the distribution.
+; 
+;  *  Neither the name of Texas Instruments Incorporated nor the names of
+;     its contributors may be used to endorse or promote products derived
+;     from this software without specific prior written permission.
+; 
+;  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+;  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+;  PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+;  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+;  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+;  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+;  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+;  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+;  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+;  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+; ******************************************************************************
+;  
+;                        MSP430 CODE EXAMPLE DISCLAIMER
+; 
+;  MSP430 code examples are self-contained low-level programs that typically
+;  demonstrate a single peripheral function or device feature in a highly
+;  concise manner. For this the code may rely on the device's power-on default
+;  register values and settings such as the clock configuration and care must
+;  be taken when combining code from several examples to avoid potential side
+;  effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware
+;  for an API functional library-approach to peripheral configuration.
+; 
+; --/COPYRIGHT--
+;*******************************************************************************
+;   MSP430F20x2 Demo - ADC10, DTC Sample A3-01, AVcc, Single Sequence, DCO
+;
+;   Description: Sample A3/A2/A1 as single sequence with reference to AVcc.
+;   Software sets ADC10SC to trigger sample sequence. In Mainloop MSP430 waits
+;   in LPM0 to save power until ADC10 conversion complete, ADC10_ISR(DTC) will
+;   force exit from any LPMx in Mainloop on reti. ADC10_ISR will force any LPMx
+;   exit. ADC10 internal oscillator times sample period (16x) and conversion
+;   (13x). DTC transfers conversion code to RAM 200h - 206h. P1.0 set at start
+;   of conversion burst, reset on completion.
+;
+;                MSP430F20x2
+;             -----------------
+;         /|\|              XIN|-
+;          | |                 |
+;          --|RST          XOUT|-
+;            |                 |
+;        >---|P1.3/A3      P1.0|-->LED
+;        >---|P1.2/A2          |
+;        >---|P1.1/A1          |
+;
+;   L. Westlund
+;   Texas Instruments Inc.
+;   May 2006
+;   Built with IAR Embedded Workbench Version: 3.41A
+;*******************************************************************************
+#include <msp430.h>
+;-------------------------------------------------------------------------------
+            RSEG    CSTACK                  ; Define stack segment
+;-------------------------------------------------------------------------------
+            RSEG    CODE                    ; Assemble to Flash memory
+;-------------------------------------------------------------------------------
+RESET       mov.w   #SFE(CSTACK),SP         ; Initialize stackpointer
+StopWDT     mov.w   #WDTPW+WDTHOLD,&WDTCTL  ; Stop WDT
+SetupADC10  mov.w   #INCH_3+CONSEQ_1,&ADC10CTL1 ; A3/A2/A1, single sequence
+            mov.w   #ADC10SHT_2+MSC+ADC10ON+ADC10IE,&ADC10CTL0 ;
+            bis.b   #0Eh,&ADC10AE0          ; P1.1,2,3 ADC10 option selects
+            mov.b   #03h,&ADC10DTC1         ; 3 conversions
+SetupP1     bis.b   #001h,&P1DIR            ; P1.0 output
+                                            ;
+Mainloop    bic.w   #ENC,&ADC10CTL0         ;
+busy_test   bit     #BUSY,&ADC10CTL1        ; ADC10 core inactive?
+            jnz     busy_test               ;
+            mov.w   #0200h,&ADC10SA         ; Data buffer start
+            bis.b   #001h,&P1OUT            ; P1.0 = 0
+            bis.w   #ENC+ADC10SC,&ADC10CTL0 ; Start sampling
+            bis.w   #CPUOFF+GIE,SR          ; LPM0, ADC10_ISR will force exit
+            bic.b   #001h,&P1OUT            ; P1.0 = 1
+            jmp     Mainloop                ; Again
+                                            ;
+;-------------------------------------------------------------------------------
+ADC10_ISR;  Exit LPM0 on reti
+;-------------------------------------------------------------------------------
+            bic.w   #CPUOFF,0(SP)           ; Exit LPM0 on reti
+            reti                            ;
+                                            ;
+;-------------------------------------------------------------------------------
+            COMMON  INTVEC                  ; Interrupt Vectors
+;-------------------------------------------------------------------------------
+            ORG     ADC10_VECTOR            ; ADC10 Vector
+            DW      ADC10_ISR
+            ORG     RESET_VECTOR            ; POR, ext. Reset
+            DW      RESET
+            END