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Imants Pulkstenis
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; --COPYRIGHT--,BSD_EX
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; Copyright (c) 2012, Texas Instruments Incorporated
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; All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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;
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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;
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the distribution.
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;
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; * Neither the name of Texas Instruments Incorporated nor the names of
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; its contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;
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; ******************************************************************************
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;
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; MSP430 CODE EXAMPLE DISCLAIMER
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;
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; MSP430 code examples are self-contained low-level programs that typically
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; demonstrate a single peripheral function or device feature in a highly
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; concise manner. For this the code may rely on the device's power-on default
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; register values and settings such as the clock configuration and care must
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; be taken when combining code from several examples to avoid potential side
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; effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware
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; for an API functional library-approach to peripheral configuration.
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;
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; --/COPYRIGHT--
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;*******************************************************************************
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; MSP430F20x2 Demo - ADC10, Output Internal Vref on P1.4 & ADCCLK on P1.3
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;
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; Description: Output ADC10 internal Vref on P1.4, toggling between two
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; available options, 2.5V and 1.5V. ADC10OSC also output on P1.3.
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;
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; MSP430F20x2
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; ----------------
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; /|\| XIN|-
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; | | |
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; --|RST XOUT|-
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; | |
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; | P1.3/ADC10CLK|--> ADC10OSC ~ 3.5MHz - 6.5MHz
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; | P1.4/A4|--> Vref
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;
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; P.Thanigai
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; Texas Instruments Inc.
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; May 2007
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; Built with Code Composer Essentials Version: 2.0
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;*******************************************************************************
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.cdecls C,LIST, "msp430.h"
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;-------------------------------------------------------------------------------
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.def RESET ; Export program entry-point to
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; make it known to linker.
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;------------------------------------------------------------------------------
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.text ; Progam Start
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;------------------------------------------------------------------------------
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RESET mov.w #0280h,SP ; Initialize stackpointer
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StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop WDT
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SetupADC10 mov.w #CONSEQ_2,&ADC10CTL1 ; Repeat single channel
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mov.w #REFOUT+REFON+MSC+ADC10ON,&ADC10CTL0; ADC10 and VRef
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mov.w #30,&TACCR0 ; Delay to allow Ref to settle
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bis.w #CCIE,&TACCTL0 ; Compare-mode interrupt.
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mov.w #TACLR+MC_1+TASSEL_2,&TACTL; up mode, SMCLK
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bis.w #LPM0+GIE,SR ; Enter LPM0, enable interrupts
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bic.w #CCIE,&TACCTL0 ; Disable timer interrupt
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dint ; Disable Interrupts
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bis.b #010h,&ADC10AE0 ; P1.4 = ADC10 option select
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bis.b #008h,&P1DIR ; P1.3 = output directon
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bis.b #008h,&P1SEL ; P1.3 = ADC10OSC option select
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;
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Mainloop bic.w #ENC,&ADC10CTL0 ; ADC10 disable
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xor.w #REF2_5V,&ADC10CTL0 ; Toggle Vref 1.5/2.5V
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bis.w #ENC+ADC10SC,&ADC10CTL0 ; ADC10 enable, start conversion
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Delay mov.w #00Fh,R15 ; Long Delay
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mov.w #0,R14 ;
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Delay_1 dec.w R14 ;
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sbc.w R15 ;
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jnz Delay_1 ;
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jmp Mainloop ;
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;
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;-------------------------------------------------------------------------------
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TA0_ISR; ISR for TACCR0
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;-------------------------------------------------------------------------------
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clr.w &TACTL ; Clear Timer_A control registers
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bic.w #LPM0,0(SP) ; Exit LPM0 on reti
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reti ;
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;------------------------------------------------------------------------------
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; Interrupt Vectors
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;------------------------------------------------------------------------------
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.sect ".reset" ; MSP430 RESET Vector
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.short RESET ;
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.sect ".int09" ; Timer_A0 Vector
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.short TA0_ISR ;
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.end
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