125 lines
2.7 KiB
Verilog
125 lines
2.7 KiB
Verilog
// This file is Test Bench for top_vga_mem module
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//
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//
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// 100MHz clock input from top module
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// 50% duty cycle 5ns HIGH and 5ns LOW
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//`timescale [time unit] / [time precision]
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`timescale 10 ns / 1ns
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//sub modules
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`include "clock_enable_param.v"
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//test modulea
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`include "default_reg_writer.v"
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`include "blockram.v"
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`include "reg_reader.v"
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module register_rd_wr_tb #(parameter
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CAM_LINE = 9,
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CAM_PIXEL = 10,
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DEPTH = 88,
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ADDR_WIDTH = 7,
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DATA_WIDTH = 25
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)();
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//--------Internal register-----------
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reg clk = 1'b0;
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wire w_enable;
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reg reset = 0;
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wire [24:0] w_data_reg;
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wire [6:0] w_addr_rd_reg;
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wire w_config_default ;
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wire [6:0] w_addr_default ;
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wire [24:0] w_data_default ;
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wire w_we_default ;
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//---------Test script----------------
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// 50% duty cycle clock
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always #0.5 clk <= ~clk;
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//-----Unit Under test---------------
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default_reg_writer #(
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.CAM_LINE(CAM_LINE),
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.CAM_PIXEL(CAM_PIXEL)
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) default_reg_writer1(
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.clk(clk),
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.i_enable(w_enable),
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.i_reset(reset),
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.o_configured(w_config_default),
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.o_addr(w_addr_default),
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.o_data(w_data_default) ,
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.o_we(w_we_default)
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);
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reg_reader #(
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.CAM_LINE(CAM_LINE),
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.CAM_PIXEL(CAM_PIXEL)
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) reg_reader1 (
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.clk(clk),
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.i_enable(w_enable),
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.i_cam0_mode(2'b00),
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.i_cam1_mode(2'b00),
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.i_data(w_data_reg),
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.o_addr_rd(w_addr_rd_reg)
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);
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rams_tdp_rf_rf #(
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.DEPTH(DEPTH),
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH)
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)
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bram_reg(
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// -------------------------PORT A
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.clka( clk),
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.ena(1'b1),
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.wea( ),
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.addra(w_addr_rd_reg),
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.dia( ),
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.doa(w_data_reg),
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//---------------------------PORT B
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.clkb( clk),
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.addrb( w_config_default ? w_addr_default : w_addr_default ),
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.enb( w_enable),
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.web( w_config_default ? w_we_default : w_we_default),
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.dib( w_config_default ? w_data_default : w_data_default),
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.dob() // not connected
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);
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//------sub modules-------------------
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clock_enable_param #(
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// .WAIT(WAIT),
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// .WIDTH(WAIT_WIDTH)
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) clock_enable1 (
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.clk(clk),
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.enable(w_enable)
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);
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initial
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begin
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#0_500;
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$display("*");
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reset = 1;
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#0_020;
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reset = 0;
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#3_500;
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$display(" ");
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$display("Use this command to open timing diagram:");
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$display("gtkwave -f wave.vcd");
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$display("----------------------------------------------");
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$finish();
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end
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initial
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begin
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$display(" ");
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$display("----------------------------------------------");
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$display(" Starting Testbench...");
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$dumpfile("wave.vcd");
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$dumpvars(0);
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end
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endmodule |