Add Quartus project
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Imants Pulkstenis
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/*****************************************************************************
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* *
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* Module: Altera_UP_PS2 *
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* Description: *
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* This module communicates with the PS2 core. *
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* *
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*****************************************************************************/
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module PS2_Controller #(parameter INITIALIZE_MOUSE = 0) (
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// Inputs
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CLOCK_50,
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reset,
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the_command,
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send_command,
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// Bidirectionals
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PS2_CLK, // PS2 Clock
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PS2_DAT, // PS2 Data
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// Outputs
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command_was_sent,
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error_communication_timed_out,
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received_data,
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received_data_en // If 1 - new data has been received
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);
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/*****************************************************************************
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* Parameter Declarations *
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*****************************************************************************/
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/*****************************************************************************
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* Port Declarations *
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*****************************************************************************/
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// Inputs
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input CLOCK_50;
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input reset;
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input [7:0] the_command;
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input send_command;
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// Bidirectionals
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inout PS2_CLK;
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inout PS2_DAT;
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// Outputs
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output command_was_sent;
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output error_communication_timed_out;
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output [7:0] received_data;
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output received_data_en;
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wire [7:0] the_command_w;
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wire send_command_w, command_was_sent_w, error_communication_timed_out_w;
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generate
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if(INITIALIZE_MOUSE) begin
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assign the_command_w = init_done ? the_command : 8'hf4;
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assign send_command_w = init_done ? send_command : (!command_was_sent_w && !error_communication_timed_out_w);
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assign command_was_sent = init_done ? command_was_sent_w : 0;
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assign error_communication_timed_out = init_done ? error_communication_timed_out_w : 1;
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reg init_done;
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always @(posedge CLOCK_50)
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if(reset) init_done <= 0;
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else if(command_was_sent_w) init_done <= 1;
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end else begin
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assign the_command_w = the_command;
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assign send_command_w = send_command;
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assign command_was_sent = command_was_sent_w;
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assign error_communication_timed_out = error_communication_timed_out_w;
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end
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endgenerate
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/*****************************************************************************
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* Constant Declarations *
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*****************************************************************************/
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// states
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localparam PS2_STATE_0_IDLE = 3'h0,
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PS2_STATE_1_DATA_IN = 3'h1,
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PS2_STATE_2_COMMAND_OUT = 3'h2,
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PS2_STATE_3_END_TRANSFER = 3'h3,
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PS2_STATE_4_END_DELAYED = 3'h4;
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/*****************************************************************************
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* Internal wires and registers Declarations *
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*****************************************************************************/
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// Internal Wires
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wire ps2_clk_posedge;
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wire ps2_clk_negedge;
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wire start_receiving_data;
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wire wait_for_incoming_data;
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// Internal Registers
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reg [7:0] idle_counter;
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reg ps2_clk_reg;
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reg ps2_data_reg;
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reg last_ps2_clk;
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// State Machine Registers
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reg [2:0] ns_ps2_transceiver;
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reg [2:0] s_ps2_transceiver;
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/*****************************************************************************
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* Finite State Machine(s) *
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*****************************************************************************/
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always @(posedge CLOCK_50)
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begin
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if (reset == 1'b1)
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s_ps2_transceiver <= PS2_STATE_0_IDLE;
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else
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s_ps2_transceiver <= ns_ps2_transceiver;
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end
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always @(*)
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begin
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// Defaults
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ns_ps2_transceiver = PS2_STATE_0_IDLE;
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case (s_ps2_transceiver)
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PS2_STATE_0_IDLE:
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begin
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if ((idle_counter == 8'hFF) &&
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(send_command == 1'b1))
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ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
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else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
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ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
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else
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ns_ps2_transceiver = PS2_STATE_0_IDLE;
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end
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PS2_STATE_1_DATA_IN:
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begin
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if ((received_data_en == 1'b1)/* && (ps2_clk_posedge == 1'b1)*/)
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ns_ps2_transceiver = PS2_STATE_0_IDLE;
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else
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ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
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end
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PS2_STATE_2_COMMAND_OUT:
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begin
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if ((command_was_sent == 1'b1) ||
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(error_communication_timed_out == 1'b1))
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ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
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else
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ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
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end
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PS2_STATE_3_END_TRANSFER:
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begin
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if (send_command == 1'b0)
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ns_ps2_transceiver = PS2_STATE_0_IDLE;
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else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
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ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
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else
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ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
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end
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PS2_STATE_4_END_DELAYED:
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begin
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if (received_data_en == 1'b1)
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begin
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if (send_command == 1'b0)
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ns_ps2_transceiver = PS2_STATE_0_IDLE;
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else
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ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
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end
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else
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ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
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end
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default:
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ns_ps2_transceiver = PS2_STATE_0_IDLE;
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endcase
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end
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/*****************************************************************************
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* Sequential logic *
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*****************************************************************************/
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always @(posedge CLOCK_50)
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begin
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if (reset == 1'b1)
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begin
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last_ps2_clk <= 1'b1;
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ps2_clk_reg <= 1'b1;
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ps2_data_reg <= 1'b1;
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end
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else
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begin
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last_ps2_clk <= ps2_clk_reg;
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ps2_clk_reg <= PS2_CLK;
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ps2_data_reg <= PS2_DAT;
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end
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end
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always @(posedge CLOCK_50)
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begin
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if (reset == 1'b1)
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idle_counter <= 6'h00;
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else if ((s_ps2_transceiver == PS2_STATE_0_IDLE) &&
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(idle_counter != 8'hFF))
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idle_counter <= idle_counter + 6'h01;
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else if (s_ps2_transceiver != PS2_STATE_0_IDLE)
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idle_counter <= 6'h00;
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end
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/*****************************************************************************
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* Combinational logic *
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*****************************************************************************/
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assign ps2_clk_posedge =
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((ps2_clk_reg == 1'b1) && (last_ps2_clk == 1'b0)) ? 1'b1 : 1'b0;
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assign ps2_clk_negedge =
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((ps2_clk_reg == 1'b0) && (last_ps2_clk == 1'b1)) ? 1'b1 : 1'b0;
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assign start_receiving_data = (s_ps2_transceiver == PS2_STATE_1_DATA_IN);
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assign wait_for_incoming_data =
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(s_ps2_transceiver == PS2_STATE_3_END_TRANSFER);
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/*****************************************************************************
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* Internal Modules *
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*****************************************************************************/
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Altera_UP_PS2_Data_In PS2_Data_In (
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// Inputs
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.clk (CLOCK_50),
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.reset (reset),
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.wait_for_incoming_data (wait_for_incoming_data),
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.start_receiving_data (start_receiving_data),
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.ps2_clk_posedge (ps2_clk_posedge),
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.ps2_clk_negedge (ps2_clk_negedge),
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.ps2_data (ps2_data_reg),
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// Bidirectionals
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// Outputs
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.received_data (received_data),
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.received_data_en (received_data_en)
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);
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Altera_UP_PS2_Command_Out PS2_Command_Out (
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// Inputs
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.clk (CLOCK_50),
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.reset (reset),
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.the_command (the_command_w),
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.send_command (send_command_w),
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.ps2_clk_posedge (ps2_clk_posedge),
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.ps2_clk_negedge (ps2_clk_negedge),
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// Bidirectionals
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.PS2_CLK (PS2_CLK),
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.PS2_DAT (PS2_DAT),
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// Outputs
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.command_was_sent (command_was_sent_w),
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.error_communication_timed_out (error_communication_timed_out_w)
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);
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endmodule
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