41 lines
899 B
Verilog
41 lines
899 B
Verilog
// Code from:
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// Vivado Design Suite
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// User Guide
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// Synthesis
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// UG901 (v2018.3) December 19, 2018
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//
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// Dual-Port Block RAM with Two Write Ports
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// File: rams_tdp_rf_rf.v
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module blockram #( parameter
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DEPTH = 4_800,//307_200,//76_800,
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ADDR_WIDTH = 13,
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DATA_WIDTH = 12 ) (clka,clkb,ena,enb,wea,web,addra,addrb,dia,dib,doa,dob);
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input clka,clkb,ena,enb,wea,web;
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input [ADDR_WIDTH-1:0] addra,addrb;
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input [DATA_WIDTH-1:0] dia,dib;
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output [DATA_WIDTH-1:0] doa,dob;
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//reg [ADDR_WIDTH-1:0] ram [ DEPTH - 1 :0];
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reg [DATA_WIDTH-1:0] ram [ DEPTH - 1 :0];
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reg [DATA_WIDTH-1:0] doa,dob;
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always @(posedge clka)
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begin
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if (ena)
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begin
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if (wea)
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ram[addra] <= dia;
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doa <= ram[addra];
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end
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end
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always @(posedge clkb)
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begin
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if (enb)
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begin
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if (web)
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ram[addrb] <= dib;
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dob <= ram[addrb];
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end
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end
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endmodule |