Writing test pattern for VGA to multiple BRAM

Basys3_Master.xdc

@@ -13,12 +13,12 @@ set_property PACKAGE_PIN W5 [get_ports clk]
 	create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
  
 ## Switches
-set_property PACKAGE_PIN V17 [get_ports {sw[0]}]					
+#set_property PACKAGE_PIN V17 [get_ports {sw[0]}]					
-	set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
+#	set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
-set_property PACKAGE_PIN V16 [get_ports {sw[1]}]					
+#set_property PACKAGE_PIN V16 [get_ports {sw[1]}]					
-	set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
+#	set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
-set_property PACKAGE_PIN W16 [get_ports {sw[2]}]					
+#set_property PACKAGE_PIN W16 [get_ports {sw[2]}]					
-	set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
+#	set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
 #set_property PACKAGE_PIN W17 [get_ports {sw[3]}]					
 	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
 #set_property PACKAGE_PIN W15 [get_ports {sw[4]}]					
@@ -83,32 +83,32 @@ set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
 	
 	
 ##7 segment display
-set_property PACKAGE_PIN W7 [get_ports {seg[0]}]					
+#set_property PACKAGE_PIN W7 [get_ports {seg[0]}]					
-	set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
+#	set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
-set_property PACKAGE_PIN W6 [get_ports {seg[1]}]					
+#set_property PACKAGE_PIN W6 [get_ports {seg[1]}]					
-	set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
+#	set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
-set_property PACKAGE_PIN U8 [get_ports {seg[2]}]					
+#set_property PACKAGE_PIN U8 [get_ports {seg[2]}]					
-	set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
+#	set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
-set_property PACKAGE_PIN V8 [get_ports {seg[3]}]					
+#set_property PACKAGE_PIN V8 [get_ports {seg[3]}]					
-	set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
+#	set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
-set_property PACKAGE_PIN U5 [get_ports {seg[4]}]					
+#set_property PACKAGE_PIN U5 [get_ports {seg[4]}]					
-	set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
+#	set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
-set_property PACKAGE_PIN V5 [get_ports {seg[5]}]					
+#set_property PACKAGE_PIN V5 [get_ports {seg[5]}]					
-	set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
+#	set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
-set_property PACKAGE_PIN U7 [get_ports {seg[6]}]					
+#set_property PACKAGE_PIN U7 [get_ports {seg[6]}]					
-	set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
+#	set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
 
-#set_property PACKAGE_PIN V7 [get_ports dp]							
+##set_property PACKAGE_PIN V7 [get_ports dp]							
-	#set_property IOSTANDARD LVCMOS33 [get_ports dp]
+#	#set_property IOSTANDARD LVCMOS33 [get_ports dp]
 
-set_property PACKAGE_PIN U2 [get_ports {an[0]}]					
+#set_property PACKAGE_PIN U2 [get_ports {an[0]}]					
-	set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
+#	set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
-set_property PACKAGE_PIN U4 [get_ports {an[1]}]					
+#set_property PACKAGE_PIN U4 [get_ports {an[1]}]					
-	set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
+#	set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
-set_property PACKAGE_PIN V4 [get_ports {an[2]}]					
+#set_property PACKAGE_PIN V4 [get_ports {an[2]}]					
-	set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
+#	set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
-set_property PACKAGE_PIN W4 [get_ports {an[3]}]					
+#set_property PACKAGE_PIN W4 [get_ports {an[3]}]					
-	set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
+#	set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
 
 
 ##Buttons
@@ -268,10 +268,10 @@ set_property PACKAGE_PIN R19 [get_ports Vsync]
 
 
 ##USB-RS232 Interface
-set_property PACKAGE_PIN B18 [get_ports RsRx]						
+#set_property PACKAGE_PIN B18 [get_ports RsRx]						
-	set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
+#	set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
-set_property PACKAGE_PIN A18 [get_ports RsTx]						
+#set_property PACKAGE_PIN A18 [get_ports RsTx]						
-	set_property IOSTANDARD LVCMOS33 [get_ports RsTx]
+#	set_property IOSTANDARD LVCMOS33 [get_ports RsTx]
 
 
 ##USB HID (PS/2)

mux.v

@@ -41,7 +41,7 @@ begin
        'd12 : q <= d12;
        'd13 : q <= d13;
        'd14 : q <= d14;
-       default : q <= 12'd0;
+       default : q <= d0;
    endcase
 end
 

mux_tb.v

@@ -0,0 +1,88 @@
+`timescale 10 ns / 1ns
+
+`include "mux.v"
+
+
+module mux_tb#( parameter 
+    SELECT_WIDTH = 4,
+    DATA_WIDTH = 12
+) ();
+
+reg [DATA_WIDTH-1:0] w_data_rd = 10;
+reg [DATA_WIDTH-1:0] w_data_rd0 = 14;
+reg [DATA_WIDTH-1:0] w_data_rd1 = 4;
+reg [DATA_WIDTH-1:0] w_data_rd2 = 23;
+reg [DATA_WIDTH-1:0] w_data_rd3 = 5;
+reg [DATA_WIDTH-1:0] w_data_rd4 = 6;
+reg [DATA_WIDTH-1:0] w_data_rd5 = 8;
+reg [DATA_WIDTH-1:0] w_data_rd6 = 12;
+reg [DATA_WIDTH-1:0] w_data_rd7 = 23;
+reg [DATA_WIDTH-1:0] w_data_rd8 = 23;
+reg [DATA_WIDTH-1:0] w_data_rd9 = 1;
+reg [DATA_WIDTH-1:0] w_data_rd10 = 2;
+reg [DATA_WIDTH-1:0] w_data_rd11 = 3;
+reg [DATA_WIDTH-1:0] w_data_rd12 = 22;
+reg [DATA_WIDTH-1:0] w_data_rd13 = 33;
+reg [DATA_WIDTH-1:0] w_data_rd14 = 44;
+reg [SELECT_WIDTH-1:0] w_vga_line_mux=0;
+
+// 50% duty cycle clock
+//always #0.5 clk <= ~clk; 
+
+initial begin
+// starting  
+// 
+
+#1 w_vga_line_mux<=1;
+#1 w_vga_line_mux<=2;
+#1 w_vga_line_mux<=3;
+#1 w_vga_line_mux<=4;
+#1 w_vga_line_mux<=5;
+#1 w_vga_line_mux<=6;
+#1 w_vga_line_mux<=7;
+#1 w_vga_line_mux<=8;
+#1 w_vga_line_mux<=9;
+#1 w_vga_line_mux<=10;
+
+
+
+    $display(" ");
+    $display("Use this command to open timing diagram:");
+    $display("gtkwave -f wave.vcd");
+    $display("----------------------------------------------");
+    $finish();
+end
+
+initial 
+  begin 
+    $display(" ");
+    $display("----------------------------------------------");
+    $display("          Starting Testbench...");
+    $dumpfile("wave.vcd");
+    $dumpvars(0);
+
+end
+
+mux #(
+    .DATA_WIDTH(DATA_WIDTH), 
+    .SELECT_WIDTH(SELECT_WIDTH)) 
+UnitUnderTest(
+    .select(w_vga_line_mux),
+    .d0(w_data_rd0),
+    .d1(w_data_rd1),
+    .d2(w_data_rd2),
+    .d3(w_data_rd3),
+    .d4(w_data_rd4),
+    .d5(w_data_rd5),
+    .d6(w_data_rd6),
+    .d7(w_data_rd7),
+    .d8(w_data_rd8),
+    .d9(w_data_rd9),
+    .d10(w_data_rd10),
+    .d11(w_data_rd11),
+    .d12(w_data_rd12),
+    .d13(w_data_rd13),
+    .d14(w_data_rd14),
+    .o_q());
+
+endmodule

pattern_gen.v

@@ -2,8 +2,8 @@
 // BlockRAM memory
 //
 module pattern_gen #( parameter
-    LINES = 480,
+    LINES = 16,
-    COLUMNS = 640,
+    COLUMNS = 320,
     DEPTH =  76_800, //307_200, //
     ADDR_WIDTH = 17,
     DATA_WIDTH = 12,
@@ -12,48 +12,35 @@ module pattern_gen #( parameter
 )(  
     input clk,
     input i_enable,
- //   input sw,
     output [ADDR_WIDTH-1:0] o_addr,
     output [DATA_WIDTH-1:0] o_data,
     output o_write);
 
 //-------------Internal Constants---------------------------
-//reg [ADDR_WIDTH-1:0] counter_reg = 'b0;
 reg [31:0] speed_counter_reg = 'b0;
-//reg [DATA_WIDTH-1:0] color_reg = 'b0;
 
-reg [3:0] red_reg = 'b0;
+// reg [3:0] red_reg = 'b0;
-reg [3:0] blue_reg = 'b0;
+// reg [3:0] blue_reg = 'b0;
-reg [3:0] green_reg = 'b0;
+// reg [3:0] green_reg = 'b0;
 
 reg [8:0] line_reg = 'b0;
 reg [9:0] column_reg = 'b0;
 
 reg write_reg=1'b0;
-/*
-localparam [SIZE-1:0]   GREEN         = 'h0,
-                        RED           = 'h1,
-                        BLUE          = 'h2;
-reg [SIZE-1:0] state_reg=GREEN, next_reg=GREEN;
 
+// always @(posedge clk) begin
+//     speed_counter_reg <= speed_counter_reg + 1;
+// end
 
-//---------state register sequential always block-----------
-always @(posedge clk ) begin
-    if (i_enable) begin
-        state_reg <= next_reg;
-    end 
-end
-*/
-//----next state & outputs, combinational always block------
 
 always @(posedge clk) begin
-    speed_counter_reg <= speed_counter_reg + 1;
+//    speed_counter_reg <= speed_counter_reg + 1;
     
-    if(speed_counter_reg == SPEED) begin
+ //   if(speed_counter_reg == SPEED ) begin
+      //  if(i_enable) begin
         write_reg <= 1'b1;
         speed_counter_reg <= 0;
-        if(i_enable) begin
+        
-        //    counter_reg <= counter_reg + 1;
             if(column_reg < COLUMNS-1) begin 
                 column_reg <= column_reg + 1 ;
             end
@@ -66,85 +53,32 @@ always @(posedge clk) begin
                     line_reg <= 0;
                 end
             end 
-/*
-        if (line_reg < 239 ) begin
-            green_reg <= 4'b1111;
-        end
-        else begin
-            green_reg <= 4'b0000;
-        end
-*/
 
-/*
+       // end
-        if (column_reg < 319 || column_reg  == 639) begin
+    // end
-            red_reg <= 4'b1111;
+    // else // if (i_enable) 
-        end
+    //     write_reg <= 1'b0;
-        else begin
-            red_reg <= 4'b0000;
-        end
-*/
-        
-
-/*
-        case (state_reg)
-        GREEN : begin
-      
-            color_reg <= 12'b111100000000;
-            if(counter_reg == DEPTH - 1) begin
-                next_reg <= RED;
-                counter_reg <= 'b0;
-            end
-        end
-      
-        RED : begin
-      
-            color_reg <= 12'b000011110000;
-            if(counter_reg == DEPTH - 1 ) begin
-                next_reg <= BLUE;
-                counter_reg <= 'b0;
-            end
-        end
-      
-        BLUE : begin
-      
-            color_reg <= 12'b000000001111;
-            if(counter_reg == DEPTH - 1) begin
-                next_reg <= GREEN;
-                counter_reg <= 'b0;
-            end
-        end
-      
-        default: begin
-                next_reg <= GREEN ;
-                counter_reg <= 'b0;
-            end
-        endcase
-*/
-        end
-    end
-    else if (i_enable) write_reg <= 1'b0;
 end
 
-always@* begin
+// always@* begin
-        if (line_reg < 239 ) begin
+//         if (line_reg < 239 ) begin
-            green_reg <= 4'b1111;
+//             green_reg <= 4'b1111;
-        end
+//         end
-        else begin
+//         else begin
-            green_reg <= 4'b0000;
+//             green_reg <= 4'b0000;
-        end
+//         end
 
-        if (column_reg > 319 ) begin
+//         if (column_reg > 319 ) begin
-            red_reg <= 4'b1111;
+//             red_reg <= 4'b1111;
-        end
+//         end
-        else begin
+//         else begin
-            red_reg <= 4'b0000;
+//             red_reg <= 4'b0000;
-        end
+//         end
-end
+// end
 
 
-assign o_addr = (line_reg[8:1] * COLUMNS/2) + column_reg [9:1] ;
+assign o_addr = (line_reg * COLUMNS) + column_reg ;
-assign o_data = {green_reg, red_reg , blue_reg};
+assign o_data = {line_reg[3:0], line_reg[3:0], line_reg[3:0]};//{green_reg, red_reg , blue_reg};
-//assign o_write = sw ? write_reg : 1'b0 ;              // remowing switch
 assign o_write = write_reg;
 
 endmodule

top.v

@@ -31,14 +31,14 @@ module top #( parameter
     output [3:0]    vgaBlue,
     output [3:0]    vgaGreen,
     output          Hsync,
-    output          Vsync,
+    output          Vsync//,
-    input [2:0]     sw,
+    // input [2:0]     sw,
-    //UART 
+    // //UART 
-    input           RsRx,         // UART RX Data
+    // input           RsRx,         // UART RX Data
-    output          RsTx,        // UART TX Data
+    // output          RsTx,        // UART TX Data
-    // 7 segment
+    // // 7 segment
-    output  [6:0]   seg, 
+    // output  [6:0]   seg, 
-    output  [3:0]   an  
+    // output  [3:0]   an  
     );
 
 //------internal wires and registers--------
@@ -56,7 +56,7 @@ wire [ADDR_WIDTH-1:0] w_com_addr_rd;
 
 wire [3:0] w_vga_line_mux;
 
-//  wire [ADDR_WIDTH-1:0] w_addrb;
+wire [ADDR_WIDTH-1:0] w_addr_rd;
 
 wire [DATA_WIDTH-1:0] w_data_rd;
 wire [DATA_WIDTH-1:0] w_data_rd0;
@@ -100,7 +100,6 @@ pattern_gen #(
     .SPEED(SPEED)
 ) pattern_gen1 (
     .clk(clk),
-//    .sw(sw[1]),
     .i_enable(w_enable),
     .o_addr(w_addr_wr),
     .o_data(w_data_wr),
@@ -132,7 +131,7 @@ vga_module #(
     .o_display(),
     .o_line_mux(w_vga_line_mux),
     .o_addr_rd(w_addr_rd),
-    .o_data_rd(r_data_rd)
+    .i_data_rd(w_data_rd)
    );
 
 // com_to_mem #( 
@@ -169,23 +168,23 @@ mux #(
     .DATA_WIDTH(DATA_WIDTH), 
     .SELECT_WIDTH('d4)) 
 mux1(
-    select(w_vga_line_mux),
+    .select(w_vga_line_mux),
-    d0(w_data_rd0),
+    .d0(w_data_rd0),
-    d1(w_data_rd1),
+    .d1(w_data_rd1),
-    d2(w_data_rd2),
+    .d2(w_data_rd2),
-    d3(w_data_rd3),
+    .d3(w_data_rd3),
-    d4(w_data_rd4),
+    .d4(w_data_rd4),
-    d5(w_data_rd5),
+    .d5(w_data_rd5),
-    d6(w_data_rd6),
+    .d6(w_data_rd6),
-    d7(w_data_rd7),
+    .d7(w_data_rd7),
-    d8(w_data_rd8),
+    .d8(w_data_rd8),
-    d9(w_data_rd9),
+    .d9(w_data_rd9),
-    d10(w_data_rd10),
+    .d10(w_data_rd10),
-    d11(w_data_rd11),
+    .d11(w_data_rd11),
-    d12(w_data_rd12),
+    .d12(w_data_rd12),
-    d13(w_data_rd13),
+    .d13(w_data_rd13),
-    d14(w_data_rd14),
+    .d14(w_data_rd14),
-    q(w_data_rd));
+    .o_q(w_data_rd));
 
 
 

top_tb.v

@@ -15,547 +15,71 @@
 `include "vga_module.v"
 `include "horizontal_counter.v"
 `include "vertical_counter.v"
-`include "UART_Loopback_module.v"
+// `include "UART_Loopback_module.v"
-`include "UART_TX.v"
+// `include "UART_TX.v"
-`include "UART_RX.v"
+// `include "UART_RX.v"
-`include "7segment.v"
+// `include "7segment.v"
-`include "com_to_mem_FSM_hex.v" 
+// `include "com_to_mem_FSM_hex.v" 
-`include "com_to_mem_module.v"
+// `include "com_to_mem_module.v"
-`include "debounce_switch.v"
+// `include "debounce_switch.v"
+`include "mux.v"
 
 
 //top module
 `include "top.v"
 
-module top_vga_mem_tb#( parameter
+module top_tb#( parameter
     WAIT = 1,
-    WAIT_WIDTH = 2,
+    WAIT_WIDTH = 2//,
-    SPEED = 2,
+    // SPEED = 2,
-     //memory parameters
+    //  //memory parameters
-    ADDR_WIDTH = 17, //19, // 
+    // ADDR_WIDTH = 17, //19, // 
-    DATA_WIDTH = 12, 
+    // DATA_WIDTH = 12, 
-    DEPTH =  307_200//76_800, // 
+    // DEPTH =  307_200//76_800, // 
 )();
 
 reg clk = 1'b0;
-reg pclk = 1'b0;
+// reg pclk = 1'b0;
-reg hs = 1'b0;
+// reg hs = 1'b0;
-reg vs = 1'b0;
+// reg vs = 1'b0;
 
 // 50% duty cycle clock
 always #0.5 clk <= ~clk;
-always #2 pclk <= ~pclk;
+// always #2 pclk <= ~pclk;
-always #100 hs <= 1;
+// always #100 hs <= 1;
-always #102 hs <= 0;
+// always #102 hs <= 0;
-always #200 vs <= 1;
+// always #200 vs <= 1;
-always #202 vs <= 0;
+// always #202 vs <= 0;
 
-reg RsRx;
+// reg RsRx;
-wire RsTx;
+// wire RsTx;
 
-top_vga_mem #(
+top #(
-    .SPEED(SPEED),
+    // .SPEED(SPEED),
-    .ADDR_WIDTH(ADDR_WIDTH),
+    // .ADDR_WIDTH(ADDR_WIDTH),
-    .DATA_WIDTH(DATA_WIDTH),
+    // .DATA_WIDTH(DATA_WIDTH),
-    .DEPTH(DEPTH)
+    // .DEPTH(DEPTH)
 )Test_Unit(
-    .clk(clk), 
+    .clk(clk)//, 
-    .RsRx(RsRx),
+    // .RsRx(RsRx),
-    .RsTx(RsTx),
+    // .RsTx(RsTx),
-    .sw(3'b101),
+    // .sw(3'b101),
-    .ov7670_cam1_pclk(pclk),
+    // .ov7670_cam1_pclk(pclk),
-    .ov7670_cam2_pclk(pclk),
+    // .ov7670_cam2_pclk(pclk),
-    .ov7670_cam1_vs(vs),
+    // .ov7670_cam1_vs(vs),
-    .ov7670_cam1_hs(hs),
+    // .ov7670_cam1_hs(hs),
-    .ov7670_cam2_vs(vs),
+    // .ov7670_cam2_vs(vs),
-    .ov7670_cam2_hs(hs),
+    // .ov7670_cam2_hs(hs),
-    .im_p(9'b00_01_01_000)  
+    // .im_p(9'b00_01_01_000)  
 );
 
-initial begin
+// initial begin
-// starting UART transition
-// h70  ->  P
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-// h30  ->  0
-    #9000;
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
 
-// h32  ->  2
+// end
-    #9000;
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-
-// h30  ->  0
-    #9000;
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-
-// h30  ->  0
-    #9000;
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-
-// h30  ->  0
-    #9000;
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-
-// h30  ->  0
-    #9000;
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-
-// h30  ->  0
-    #9000;
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-
-// h63  ->  c
-    #9000;
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-
-    #868 RsRx = 1;
-
-// h38  ->  8
-    #9000;
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-
-    #868 RsRx = 1;
-
-    #10_000;
-
-// h72  ->  r
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-// h30  ->  0
-    #9000;
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-
-// h30  ->  0
-    #9000;
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-
-// h30  ->  0
-    #9000;
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-
-
-// h35  ->  5
-    #9000;
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-
-// h35  ->  5
-    #9000;
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-
- #10_000;
-
-// h70  ->  p
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-// h30  ->  0
-    #9000;
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-
-// h30  ->  0
-    #9000;
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-
-// h30  ->  0
-    #9000;
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-
-// h35  ->  5
-    #9000;
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-
-// h35  ->  5
-    #9000;
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-
-// h32  ->  2
-    #9000;
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-
-// h35  ->  5
-    #9000;
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-
-// h35  ->  5
-    #9000;
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-
-    #10_000;
-
-// h72  ->  r
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-// h30  ->  0
-    #9000;
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-
-// h30  ->  0
-    #9000;
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-
-// h30  ->  0
-    #9000;
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-
-// h35  ->  5
-    #9000;
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-
-// h35  ->  5
-    #9000;
-    #0 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-    #868 RsRx = 1;
-    #868 RsRx = 0;
-    #868 RsRx = 0;
-    #868 RsRx = 1;
-
-    #10_000;
-
-end
 
 
 initial begin
-    #000_001;
+
-    $display("*");
-    #030_000; 
-    $display("*");
-    #030_000; 
-    $display("*");
-    #030_000; 
-    $display("*");
-    #030_000; 
-    $display("*");
-    #030_000; 
-    $display("*");
-    #030_000; 
-    $display("*");
-    #030_000; 
-    $display("*");
-    #030_000; 
-    $display("*");
-    #030_000; 
-    $display("*");
-    #030_000; 
-    $display("*");
-    #030_000; 
-    $display("*");
-    #030_000; 
-    $display("*");
-    #030_000; 
-    $display("*");
-    #030_000; 
-    $display("*");
-    #030_000; 
-    $display("*");
-    #030_000; 
-    $display("*");
-    #030_000; 
-    $display("*");
-    #030_000; 
     $display("*");
     #030_000; 
     $display("*");

vga_module.v

@@ -23,7 +23,7 @@ module vga_module#(
         output o_display,
         output [3:0] o_line_mux,
         output [ADDR_WIDTH-1:0] o_addr_rd,
-        input [DATA_WIDTH-1:0] o_data_rd
+        input [DATA_WIDTH-1:0] i_data_rd
         );
 
 //-------Internal registers and wires--------------
@@ -62,9 +62,9 @@ vertical_counter #(
         );
 
 assign o_display = (w_v_display && w_h_display) ;
-assign o_vgaRed = o_display ? o_data_rd[11:8] : 4'h0;
+assign o_vgaRed = o_display ? i_data_rd[11:8] : 4'h0;
-assign o_vgaBlue = o_display ? o_data_rd[3:0] : 4'h0; 
+assign o_vgaBlue = o_display ? i_data_rd[3:0] : 4'h0; 
-assign o_vgaGreen = o_display ? o_data_rd[7:4] : 4'h0;
+assign o_vgaGreen = o_display ? i_data_rd[7:4] : 4'h0;
 
 /*
 assign o_addr_rd = (((line*HSYNC_DISPLAY) + column + 1) == HSYNC_DISPLAY * VSYNC_DISPLAY ) ?