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Imants Pulkstenis
2019-07-12 12:19:06 +03:00
parent 9fa4b5ea1a
commit 37f46b5044
24 changed files with 3174 additions and 2 deletions
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7segment.v
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/*
Module was made using paper:
Coding And Scripting Techniques For FSM Designs With
Synthesis-Optimized, Glitch-Free Outputs
by Clifford E. Cummings Sunburst Design, Inc.
*/
module bin_7segment(
input clk, // clock working with 10kHz
input [15:0] sw, // switches (input)
output [6:0] seg, // individual segments of number
output [3:0] an, // anode to select character
output dp // dot on 7segment display
);
//-------------Internal Constants---------------------------
parameter SIZE = 2;
parameter [SIZE-1:0] ONE = 2'b00,
TWO = 2'b01,
THREE = 2'b10,
FOUR = 2'b11;
reg [SIZE-1:0] state=ONE, next=TWO;
reg [3:0] nibble = 'b0 ;
//---------State register sequential always block-----------
always @(posedge clk ) begin
state <= next;
end
//----Next state & outputs, combinational always block------
always@(state or sw)begin
case(state)
ONE : begin
next <= TWO;
nibble <= sw[3:0];
end
TWO : begin
next <= THREE;
nibble <= sw[7:4];
end
THREE : begin
next <= FOUR;
nibble <= sw[11:8];
end
FOUR : begin
next <= ONE;
nibble <= sw[15:12];
end
endcase
end
assign seg[6] = ( nibble == 4'h2 ||
nibble == 4'h3 ||
nibble == 4'h4 ||
nibble == 4'h5 ||
nibble == 4'h6 ||
nibble == 4'h8 ||
nibble == 4'h9 ||
nibble == 4'hA ||
nibble == 4'hB ||
nibble == 4'hD ||
nibble == 4'hE ||
nibble == 4'hF ) ? 1'b0 : 1'b1;
assign seg[5] = ( nibble == 4'h0 ||
nibble == 4'h4 ||
nibble == 4'h5 ||
nibble == 4'h6 ||
nibble == 4'h8 ||
nibble == 4'h9 ||
nibble == 4'hA ||
nibble == 4'hB ||
nibble == 4'hC ||
nibble == 4'hE ||
nibble == 4'hF ) ? 1'b0 : 1'b1;
assign seg[4] = ( nibble == 4'h0 ||
nibble == 4'h2 ||
nibble == 4'h6 ||
nibble == 4'h8 ||
nibble == 4'hA ||
nibble == 4'hB ||
nibble == 4'hC ||
nibble == 4'hD ||
nibble == 4'hE ||
nibble == 4'hF ) ? 1'b0 : 1'b1;
assign seg[3] = ( nibble == 4'h0 ||
nibble == 4'h2 ||
nibble == 4'h3 ||
nibble == 4'h5 ||
nibble == 4'h6 ||
nibble == 4'h8 ||
nibble == 4'h9 ||
nibble == 4'hB ||
nibble == 4'hC ||
nibble == 4'hD ||
nibble == 4'hE ) ? 1'b0 : 1'b1;
assign seg[2] = ( nibble == 4'h0 ||
nibble == 4'h1 ||
nibble == 4'h3 ||
nibble == 4'h4 ||
nibble == 4'h5 ||
nibble == 4'h6 ||
nibble == 4'h7 ||
nibble == 4'h8 ||
nibble == 4'h9 ||
nibble == 4'hA ||
nibble == 4'hB ||
nibble == 4'hD ) ? 1'b0 : 1'b1;
assign seg[1] = ( nibble == 4'h0 ||
nibble == 4'h1 ||
nibble == 4'h2 ||
nibble == 4'h3 ||
nibble == 4'h4 ||
nibble == 4'h7 ||
nibble == 4'h8 ||
nibble == 4'h9 ||
nibble == 4'hA ||
nibble == 4'hD ) ? 1'b0 : 1'b1;
assign seg[0] = ( nibble == 4'h0 ||
nibble == 4'h2 ||
nibble == 4'h3 ||
nibble == 4'h5 ||
nibble == 4'h6 ||
nibble == 4'h7 ||
nibble == 4'h8 ||
nibble == 4'h9 ||
nibble == 4'hA ||
nibble == 4'hC ||
nibble == 4'hE ||
nibble == 4'hF) ? 1'b0 : 1'b1;
assign dp = 1'b1; //dot
assign an[0] = (state==ONE) ? 1'b0 : 1'b1;
assign an[1] = (state==TWO) ? 1'b0 : 1'b1;
assign an[2] = (state==THREE) ? 1'b0 : 1'b1;
assign an[3] = (state==FOUR) ? 1'b0 : 1'b1;
endmodule
7segment_tb.v
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`include "7segment.v"
module bin_7segment_tb();
reg clk = 1'b0;
reg [15:0] sw = 'b0;
wire [6:0] seg;
wire [3:0] an;
wire dp;
always #1 clk <= ~clk;
always #40 sw <= sw + 1;
initial
begin
#1000;
$finish();
end
initial
begin
$display(" ");
$display("----------------------------------------------");
$display(" Starting Testbench...");
$dumpfile("wave.vcd");
$dumpvars(0);
$display("----------------------------------------------");
$display(" ");
end
bin_7segment test_unit1(
.clk(clk),
.sw(sw),
.seg(seg),
.an(an),
.dp(dp)
);
endmodule
Basys3_Master.xdc
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## This file is a general .xdc for the Basys3 rev B board
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
## Clock signal
#set_property PACKAGE_PIN W5 [get_ports clk]
#set_property IOSTANDARD LVCMOS33 [get_ports clk]
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
## Switches
#set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
#set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
#set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
#set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
#set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
#set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
#set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
#set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
#set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
#set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
#set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
#set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
#set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
#set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
#set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
#set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
## LEDs
#set_property PACKAGE_PIN U16 [get_ports {led[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
#set_property PACKAGE_PIN E19 [get_ports {led[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
#set_property PACKAGE_PIN U19 [get_ports {led[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
#set_property PACKAGE_PIN V19 [get_ports {led[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
#set_property PACKAGE_PIN W18 [get_ports {led[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
#set_property PACKAGE_PIN U15 [get_ports {led[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
#set_property PACKAGE_PIN U14 [get_ports {led[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
#set_property PACKAGE_PIN V14 [get_ports {led[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
#set_property PACKAGE_PIN V13 [get_ports {led[8]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
#set_property PACKAGE_PIN V3 [get_ports {led[9]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
#set_property PACKAGE_PIN W3 [get_ports {led[10]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
#set_property PACKAGE_PIN U3 [get_ports {led[11]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
#set_property PACKAGE_PIN P3 [get_ports {led[12]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
#set_property PACKAGE_PIN N3 [get_ports {led[13]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
#set_property PACKAGE_PIN P1 [get_ports {led[14]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
#set_property PACKAGE_PIN L1 [get_ports {led[15]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
##7 segment display
#set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
#set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
#set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
#set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
#set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
#set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
#set_property PACKAGE_PIN U7 [get_ports {seg[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
#set_property PACKAGE_PIN V7 [get_ports dp]
#set_property IOSTANDARD LVCMOS33 [get_ports dp]
#set_property PACKAGE_PIN U2 [get_ports {an[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
#set_property PACKAGE_PIN U4 [get_ports {an[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
#set_property PACKAGE_PIN V4 [get_ports {an[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
#set_property PACKAGE_PIN W4 [get_ports {an[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
##Buttons
#set_property PACKAGE_PIN U18 [get_ports btnC]
#set_property IOSTANDARD LVCMOS33 [get_ports btnC]
#set_property PACKAGE_PIN T18 [get_ports btnU]
#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
#set_property PACKAGE_PIN W19 [get_ports btnL]
#set_property IOSTANDARD LVCMOS33 [get_ports btnL]
#set_property PACKAGE_PIN T17 [get_ports btnR]
#set_property IOSTANDARD LVCMOS33 [get_ports btnR]
#set_property PACKAGE_PIN U17 [get_ports btnD]
#set_property IOSTANDARD LVCMOS33 [get_ports btnD]
##Pmod Header JA
##Sch name = JA1
#set_property PACKAGE_PIN J1 [get_ports {JA[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}]
##Sch name = JA2
#set_property PACKAGE_PIN L2 [get_ports {JA[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}]
##Sch name = JA3
#set_property PACKAGE_PIN J2 [get_ports {JA[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}]
##Sch name = JA4
#set_property PACKAGE_PIN G2 [get_ports {JA[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}]
##Sch name = JA7
#set_property PACKAGE_PIN H1 [get_ports {JA[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}]
##Sch name = JA8
#set_property PACKAGE_PIN K2 [get_ports {JA[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}]
##Sch name = JA9
#set_property PACKAGE_PIN H2 [get_ports {JA[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}]
##Sch name = JA10
#set_property PACKAGE_PIN G3 [get_ports {JA[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}]
##Pmod Header JB
##Sch name = JB1
#set_property PACKAGE_PIN A14 [get_ports {JB[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}]
##Sch name = JB2
#set_property PACKAGE_PIN A16 [get_ports {JB[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}]
##Sch name = JB3
#set_property PACKAGE_PIN B15 [get_ports {JB[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}]
##Sch name = JB4
#set_property PACKAGE_PIN B16 [get_ports {JB[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}]
##Sch name = JB7
#set_property PACKAGE_PIN A15 [get_ports {JB[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}]
##Sch name = JB8
#set_property PACKAGE_PIN A17 [get_ports {JB[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}]
##Sch name = JB9
#set_property PACKAGE_PIN C15 [get_ports {JB[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}]
##Sch name = JB10
#set_property PACKAGE_PIN C16 [get_ports {JB[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}]
##Pmod Header JC
##Sch name = JC1
#set_property PACKAGE_PIN K17 [get_ports {JC[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}]
##Sch name = JC2
#set_property PACKAGE_PIN M18 [get_ports {JC[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}]
##Sch name = JC3
#set_property PACKAGE_PIN N17 [get_ports {JC[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
##Sch name = JC4
#set_property PACKAGE_PIN P18 [get_ports {JC[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
##Sch name = JC7
#set_property PACKAGE_PIN L17 [get_ports {JC[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
##Sch name = JC8
#set_property PACKAGE_PIN M19 [get_ports {JC[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
##Sch name = JC9
#set_property PACKAGE_PIN P17 [get_ports {JC[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
##Sch name = JC10
#set_property PACKAGE_PIN R18 [get_ports {JC[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]
##Pmod Header JXADC
##Sch name = XA1_P
#set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
##Sch name = XA2_P
#set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
##Sch name = XA3_P
#set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
##Sch name = XA4_P
#set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
##Sch name = XA1_N
#set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
##Sch name = XA2_N
#set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
##Sch name = XA3_N
#set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
##Sch name = XA4_N
#set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]
##VGA Connector
#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
#set_property PACKAGE_PIN P19 [get_ports Hsync]
#set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
#set_property PACKAGE_PIN R19 [get_ports Vsync]
#set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
##USB-RS232 Interface
#set_property PACKAGE_PIN B18 [get_ports RsRx]
#set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
#set_property PACKAGE_PIN A18 [get_ports RsTx]
#set_property IOSTANDARD LVCMOS33 [get_ports RsTx]
##USB HID (PS/2)
#set_property PACKAGE_PIN C17 [get_ports PS2Clk]
#set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
#set_property PULLUP true [get_ports PS2Clk]
#set_property PACKAGE_PIN B17 [get_ports PS2Data]
#set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]
#set_property PULLUP true [get_ports PS2Data]
##Quad SPI Flash
##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
##STARTUPE2 primitive.
#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]
#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]
#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]
#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]
#set_property PACKAGE_PIN K19 [get_ports QspiCSn]
#set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]
README.md
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# FPGA-Mandelbrot-Set # FPGA-Mandelbrot-Set (Not finished)
Mandelbrot set visualization Mandelbrot set visualization
![picture](http://people.ece.cornell.edu/land/courses/ece5760/LABS/s2019/lab3_mandelbrot_rectangle.png)
I will try make Cornell University ECE 5760: Laboratory 3 Mandelbrot set visualization. I will try make Cornell University ECE 5760: Laboratory 3 Mandelbrot set visualization.
http://people.ece.cornell.edu/land/courses/ece5760/LABS/s2019/lab3_mandelbrot.html http://people.ece.cornell.edu/land/courses/ece5760/LABS/s2019/lab3_mandelbrot.html
Lectures:
* https://www.youtube.com/watch?v=7rIjuQZSby0
* https://www.youtube.com/watch?v=vxSoiG242OA&t=911s
UART_Loopback_module.v
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//
// Original file donwloaded from nandland.com
//
// Outputs byte received from UART
//
//`include "UART_RX.v"
//`include "UART_TX.v"
module UART_Loopback_module #( parameter
DATA_WIDTH = 8
)
( input clk, // Main Clock
input loopback,
input RsRx, // UART RX Data
output RsTx, // UART TX Data
output [DATA_WIDTH-1:0] dout, // data out
output o_TX_Done, // high when transition is done
output o_RX_DV // data valid
);
wire w_TX_Active, w_TX_Serial;
wire [DATA_WIDTH-1:0] w_RX_Byte;
UART_RX #(.CLKS_PER_BIT(868)) UART_RX_Inst
(.clk(clk),
.RsRx(RsRx),
.o_RX_DV(o_RX_DV),
.o_RX_Byte(w_RX_Byte));
UART_TX #(.CLKS_PER_BIT(868)) UART_TX_Inst
(.clk(clk),
.i_TX_DV(o_RX_DV),
.i_TX_Byte(w_RX_Byte),
.o_TX_Active(w_TX_Active),
.o_TX_Serial(w_TX_Serial),
.o_TX_Done(o_TX_Done));
// drive UART line high when transmiter not active
assign RsTx = (w_TX_Active && loopback) ? w_TX_Serial : 1'b1;
assign dout = w_RX_Byte;
endmodule
UART_Loopback_tb.v
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`include "UART_Loopback_module.v"
`include "UART_TX.v"
`include "UART_RX.v"
module UART_Loopback_tb();
reg clk = 1'b1;
reg RsRx; // UART RX Data
wire RsTx; // UART TX Data
wire [7:0] dout; // data out
wire o_TX_Done; // high when transition is done
wire o_RX_DV; // data valid
always #1 clk <= ~clk;
initial begin
// starting UART transition
#0 RsRx = 1;
#1736 RsRx = 0;
#1736 RsRx = 1;
#1736 RsRx = 0;
#1736 RsRx = 1;
#1736 RsRx = 0;
#1736 RsRx = 1;
#1736 RsRx = 0;
#1736 RsRx = 1;
#1736 RsRx = 0;
#1736 RsRx = 1;
#100_000;
$finish();
end
initial
begin
$display(" ");
$display("----------------------------------------------");
$display(" Starting Testbench...");
$dumpfile("wave.vcd");
$dumpvars(0);
$display("----------------------------------------------");
$display(" ");
end
UART_Loopback_module Test_Unit(
.clk(clk),
.RsRx(RsRx),
.RsTx(RsTx),
.dout(dout),
.o_TX_Done(o_TX_Done),
.o_RX_DV(o_RX_DV)
);
endmodule
UART_RX.v
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/////////////////////////////////////////////////////////////////////
// File original code downloaded from http://www.nandland.com
/////////////////////////////////////////////////////////////////////
// This file contains the UART Receiver. This receiver is able to
// receive 8 bits of serial data, one start bit, one stop bit,
// and no parity bit. When receive is complete RsRx will be
// driven high for one clock cycle.
//
// Set Parameter CLKS_PER_BIT as follows:
// CLKS_PER_BIT = (Frequency of i_Clock)/(Frequency of UART)
// Example: 100 MHz Clock, 115200 baud UART
// (100_000_000)/(115200) = 868
//
// File source are form nandland.com
//
module UART_RX
#(parameter CLKS_PER_BIT = 868)
(
input clk,
input RsRx,
output o_RX_DV,
output [7:0] o_RX_Byte
);
localparam IDLE = 3'b000;
localparam RX_START_BIT = 3'b001;
localparam RX_DATA_BITS = 3'b010;
localparam RX_STOP_BIT = 3'b011;
localparam CLEANUP = 3'b100;
reg [9:0] r_Clock_Count = 0;
reg [2:0] r_Bit_Index = 0; //8 bits total
reg [7:0] r_RX_Byte = 0;
reg r_RX_DV = 0;
reg [2:0] r_SM_Main = 0;
// Purpose: Control RX state machine
always @(posedge clk)
begin
case (r_SM_Main)
IDLE :
begin
r_RX_DV <= 1'b0;
r_Clock_Count <= 0;
r_Bit_Index <= 0;
if (RsRx == 1'b0) // Start bit detected
r_SM_Main <= RX_START_BIT;
else
r_SM_Main <= IDLE;
end
// Check middle of start bit to make sure it's still low
RX_START_BIT :
begin
if (r_Clock_Count == (CLKS_PER_BIT)/2)
begin
if (RsRx == 1'b0)
begin
r_Clock_Count <= 0; // reset counter, found the middle
r_SM_Main <= RX_DATA_BITS;
end
else
r_SM_Main <= IDLE;
end
else
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= RX_START_BIT;
end
end // case: RX_START_BIT
// Wait CLKS_PER_BIT-1 clock cycles to sample serial data
RX_DATA_BITS :
begin
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= RX_DATA_BITS;
end
else
begin
r_Clock_Count <= 0;
r_RX_Byte[r_Bit_Index] <= RsRx;
// Check if we have received all bits
if (r_Bit_Index < 7)
begin
r_Bit_Index <= r_Bit_Index + 1;
r_SM_Main <= RX_DATA_BITS;
end
else
begin
r_Bit_Index <= 0;
r_SM_Main <= RX_STOP_BIT;
end
end
end // case: RX_DATA_BITS
// Receive Stop bit. Stop bit = 1
RX_STOP_BIT :
begin
// Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= RX_STOP_BIT;
end
else
begin
r_RX_DV <= 1'b1;
r_Clock_Count <= 0;
r_SM_Main <= CLEANUP;
end
end // case: RX_STOP_BIT
// Stay here 1 clock
CLEANUP :
begin
r_SM_Main <= IDLE;
r_RX_DV <= 1'b0;
end
default :
r_SM_Main <= IDLE;
endcase
end
assign o_RX_DV = r_RX_DV;
assign o_RX_Byte = r_RX_Byte;
endmodule // UART_RX
UART_TX.v
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//////////////////////////////////////////////////////////////////////
// File Downloaded from http://www.nandland.com
//////////////////////////////////////////////////////////////////////
// This file contains the UART Transmitter. This transmitter is able
// to transmit 8 bits of serial data, one start bit, one stop bit,
// and no parity bit. When transmit is complete o_Tx_done will be
// driven high for one clock cycle.
//
// Set Parameter CLKS_PER_BIT as follows:
// CLKS_PER_BIT = (Frequency of clk)/(Frequency of UART)
// Example: 25 MHz Clock, 115200 baud UART
// (25000000)/(115200) = 217
module UART_TX
#(parameter CLKS_PER_BIT = 217)
(
input clk,
input i_TX_DV,
input [7:0] i_TX_Byte,
output o_TX_Active,
output reg o_TX_Serial,
output o_TX_Done
);
localparam IDLE = 3'b000;
localparam TX_START_BIT = 3'b001;
localparam TX_DATA_BITS = 3'b010;
localparam TX_STOP_BIT = 3'b011;
localparam CLEANUP = 3'b100;
reg [2:0] r_SM_Main = 0;
reg [9:0] r_Clock_Count = 0;
reg [2:0] r_Bit_Index = 0;
reg [7:0] r_TX_Data = 0;
reg r_TX_Done = 0;
reg r_TX_Active = 0;
always @(posedge clk)
begin
case (r_SM_Main)
IDLE :
begin
o_TX_Serial <= 1'b1; // Drive Line High for Idle
r_TX_Done <= 1'b0;
r_Clock_Count <= 0;
r_Bit_Index <= 0;
if (i_TX_DV == 1'b1)
begin
r_TX_Active <= 1'b1;
r_TX_Data <= i_TX_Byte;
r_SM_Main <= TX_START_BIT;
end
else
r_SM_Main <= IDLE;
end // case: IDLE
// Send out Start Bit. Start bit = 0
TX_START_BIT :
begin
o_TX_Serial <= 1'b0;
// Wait CLKS_PER_BIT-1 clock cycles for start bit to finish
if (r_Clock_Count < CLKS_PER_BIT)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= TX_START_BIT;
end
else
begin
r_Clock_Count <= 0;
r_SM_Main <= TX_DATA_BITS;
end
end // case: TX_START_BIT
// Wait CLKS_PER_BIT-1 clock cycles for data bits to finish
TX_DATA_BITS :
begin
o_TX_Serial <= r_TX_Data[r_Bit_Index];
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= TX_DATA_BITS;
end
else
begin
r_Clock_Count <= 0;
// Check if we have sent out all bits
if (r_Bit_Index < 7)
begin
r_Bit_Index <= r_Bit_Index + 1;
r_SM_Main <= TX_DATA_BITS;
end
else
begin
r_Bit_Index <= 0;
r_SM_Main <= TX_STOP_BIT;
end
end
end // case: TX_DATA_BITS
// Send out Stop bit. Stop bit = 1
TX_STOP_BIT :
begin
o_TX_Serial <= 1'b1;
// Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= TX_STOP_BIT;
end
else
begin
r_TX_Done <= 1'b1;
r_Clock_Count <= 0;
r_SM_Main <= CLEANUP;
r_TX_Active <= 1'b0;
end
end // case: TX_STOP_BIT
// Stay here 1 clock
CLEANUP :
begin
r_TX_Done <= 1'b1;
r_SM_Main <= IDLE;
end
default :
r_SM_Main <= IDLE;
endcase
end
assign o_TX_Active = r_TX_Active;
assign o_TX_Done = r_TX_Done;
endmodule
blockram.v
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// Code from:
// Vivado Design Suite
// User Guide
// Synthesis
// UG901 (v2018.3) December 19, 2018
//
// Dual-Port Block RAM with Two Write Ports
// File: rams_tdp_rf_rf.v
module rams_tdp_rf_rf #( parameter
DEPTH = 307_200,//76_800,
ADDR_WIDTH = 17,
DATA_WIDTH = 8 ) (clka,clkb,ena,enb,wea,web,addra,addrb,dia,dib,doa,dob);
input clka,clkb,ena,enb,wea,web;
input [ADDR_WIDTH-1:0] addra,addrb;
input [DATA_WIDTH-1:0] dia,dib;
output [DATA_WIDTH-1:0] doa,dob;
//reg [ADDR_WIDTH-1:0] ram [ DEPTH - 1 :0];
reg [DATA_WIDTH-1:0] ram [ DEPTH - 1 :0];
reg [DATA_WIDTH-1:0] doa,dob;
always @(posedge clka)
begin
if (ena)
begin
if (wea)
ram[addra] <= dia;
doa <= ram[addra];
end
end
always @(posedge clkb)
begin
if (enb)
begin
if (web)
ram[addrb] <= dib;
dob <= ram[addrb];
end
end
endmodule
clock_divider_param.v
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// This module devide FPGA input clock
// by DIVIDER. Result is 50% duty cicle
// pulses.
//
//
module clock_divider #(
parameter DIVIDER =2,
parameter WIDTH =2
) (
input clk,
output clk_out);
reg state=1'b0, next_state=1'b1;
reg [WIDTH-1:0] counter = DIVIDER-1 ;
always@(posedge clk)begin
state <= next_state;
if ( counter == 0) begin
next_state <= ~next_state;
counter <= DIVIDER-1;
end
else if (counter >= 0 )
counter <= counter - 1;
end
assign clk_out = state;
endmodule
clock_divider_param_tb.v
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// `timescale [time unit] / [time precision]
`timescale 10 ps / 1 ps
`include "clock_divider_param.v"
module clock_divider_param_tb ();
reg clk = 1'b0;
wire enable;
always #1 clk <= ~clk;
initial
begin
#100;
$finish();
end
initial
begin
$display(" ");
$display("----------------------------------------------");
$display(" Starting Testbench...");
$dumpfile("wave.vcd");
$dumpvars(0);
$display("----------------------------------------------");
$display(" ");
end
clock_divider #(
.DIVIDER(2),
.WIDTH(2)
) test_unit1 (
.clk(clk),
.enable(enable)
);
endmodule
clock_enable_param.v
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// This module devide FPGA input clock
// by DIVIDER.
//
//
module clock_enable_param #(
parameter WAIT =1,
parameter WIDTH =1
) (
input clk,
output enable);
reg state=1'b0;
reg [WIDTH-1:0] counter = 1'b0 ;
always@(posedge clk)begin
if(counter == 0)begin
if (state == 1) begin
state <= 0;
counter <= WAIT - 1;
end
else begin
state <= 1;
counter <= 0;
end
end
else counter <= counter -1;
end
assign enable = state;
endmodule
clock_enable_tb.v
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`include "clock_enable_param.v"
module clock_enable_tb();
reg clk = 1'b0;
wire enable0;
wire enable1;
wire enable2;
wire enable3;
always #1 clk <= ~clk;
initial
begin
#100;
$finish();
end
initial
begin
$display(" ");
$display("----------------------------------------------");
$display(" Starting Testbench...");
$dumpfile("wave.vcd");
$dumpvars(0);
$display("----------------------------------------------");
$display(" ");
end
clock_enable_param test_unit0(
.clk(clk),
.enable(enable0)
);
clock_enable_param #(
.WAIT(2),
.WIDTH(4)
) test_unit1(
.clk(clk),
.enable(enable1)
);
clock_enable_param #(
.WAIT(3),
.WIDTH(8)
)test_unit2(
.clk(clk),
.enable(enable2)
);
clock_enable_param #(
.WAIT(9),
.WIDTH(8)
)test_unit3(
.clk(clk),
.enable(enable3)
);
endmodule
com_to_mem_FSM_hex.v
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// Address are in decimal
// value of memory in hex
//
//
module com_to_mem_FSM#( parameter
ADDR_WIDTH = 17,
DATA_WIDTH = 12,
DEPTH = 76_800,
SIZE = 4 // size for for registers FSM
)(
input clk,
input i_enable,
input [7:0] din,
input TX_Done,
input i_RX_DV,
output [3:0] o_state,
output [3:0] o_byte,
output [ADDR_WIDTH-1:0] addr_wr,
output [ADDR_WIDTH-1:0] addr_rd,
output [DATA_WIDTH-1:0] data_wr,
output write,
// output for writing to register memory
output [6:0] o_addr_wr_reg,
output [24:0] o_data_reg,
output o_we_reg
);
//-------------Internal Constants---------------------------
localparam [SIZE-1:0] IDLE = 'h0,
GET_ADDR_W = 'h1,
GET_VALUE_W = 'h2,
WRITE_MEM = 'h3,
GET_ADDR_R = 'h4,
READ_MEM = 'h5,
GET_ADDR_W_REG = 'h6,
GET_VALUE_W_REG = 'h7,
WRITE_MEM_REG = 'h8;
reg [SIZE-1:0] r_state=IDLE,
r_next=IDLE;
reg [2:0] r_addr_byte = 3'h0;
reg [2:0] r_value_byte = 3'h0;
reg r_RX_DV = 1'b0;
reg r_RX_DV_OLD = 1'b0;
reg r_RX_DV_done = 1'b0;
// reg for main memory
reg [ADDR_WIDTH-1:0] r_addr_wr = 'b0;
reg [ADDR_WIDTH-1:0] r_addr_rd = 'b0;
reg [DATA_WIDTH-1:0] r_data_wr = 'b0;
reg r_write = 1'b0;
// reg for register memory
reg [6:0] r_addr_wr_reg = 'b0;
reg [24:0] r_data_reg = 'b0;
reg r_we_reg = 1'b0;
//---------state register sequential always block-----------
always @(posedge clk ) begin
if (i_enable) begin
r_state <= r_next;
end
end
//----next state & outputs, combinational always block------
always@(posedge clk) begin
if ( r_RX_DV == 0 ) begin
r_RX_DV <= i_RX_DV;
end
if (r_RX_DV || r_state == READ_MEM || r_state == WRITE_MEM || r_state == WRITE_MEM_REG ) begin
if (i_enable) begin
case(r_state)
IDLE : begin
if (din==8'h70 && r_RX_DV_OLD == 1'b0 ) // if p
begin
r_next <= GET_ADDR_W;
r_addr_byte <= 'h0;
r_data_wr <= 'h0;
r_addr_wr <= 'h0;
end
else if (din==8'h72 && r_RX_DV_OLD == 1'b0 ) // if r
begin
r_next <= GET_ADDR_R;
r_addr_byte <= 'h0;
r_addr_rd <= 'h0;
end
else if (din==8'h50 && r_RX_DV_OLD == 1'b0 ) // if P
begin
r_next <= GET_ADDR_W_REG;
r_addr_byte <= 'h0;
r_addr_wr_reg <= 'h0;
r_data_reg <= 'h0;
end
end
GET_ADDR_W : begin
if (r_RX_DV_OLD == 1'b0 &&
((din >= 8'h30 && din < 8'h3A) || // if 0-9
(din >= 8'h61 && din <= 8'h66) ) // if a-f
&& r_addr_byte < 'h4 )
begin
if (din >= 8'h30 && din < 8'h3A) begin // if 0-9
r_addr_wr = r_addr_wr * 'd10 + din - 'h30 ;
r_addr_byte <= r_addr_byte + 1;
end
end
else if
(r_RX_DV_OLD == 1'b0 &&
((din >= 8'h30 && din < 8'h3A) || // if 0-9
(din >= 8'h61 && din <= 8'h66) ) // if a-f
&& r_addr_byte == 'h4)
begin
if (din >= 8'h30 && din < 8'h3A) begin // if 0-9
r_addr_wr = r_addr_wr * 'd10 + din - 'h30 ;
r_value_byte <= 'b0;
r_next <= GET_VALUE_W;
end
end
end
GET_VALUE_W : begin
if (r_RX_DV_OLD == 1'b0 &&
((din >= 8'h30 && din < 8'h3A) || // if 0-9
(din >= 8'h61 && din <= 8'h66) ) // if a-f
&& r_value_byte < 'd2 )
begin
if (din >= 8'h30 && din < 8'h3A) begin // if 0-9
r_data_wr = r_data_wr * 'h10 + din - 'h30 ;
r_value_byte <= r_value_byte + 1;
end
else if (din >= 8'h61 && din <= 8'h66) begin // if a-f
r_data_wr = r_data_wr * 'h10 + din - 'h57 ;
r_value_byte <= r_value_byte + 1;
end
end
else if
(r_RX_DV_OLD == 1'b0 &&
((din >= 8'h30 && din < 8'h3A) || // if 0-9
(din >= 8'h61 && din <= 8'h66) ) // if a-f
&& r_value_byte == 'd2)
begin
if (din >= 8'h30 && din < 8'h3A) begin // if 0-9
r_data_wr = r_data_wr * 'h10 + din - 'h30 ;
r_write <= 1'b1;
r_next <= WRITE_MEM;
end
else if (din >= 8'h61 && din <= 8'h66) begin // if a-f
r_data_wr = r_data_wr * 'h10 + din - 'h57 ;
r_write <= 1'b1;
r_next <= WRITE_MEM;
end
end
end
WRITE_MEM : begin
r_write <= 1'b0;
r_addr_byte <= 0;
r_value_byte <= 0;
r_next <= IDLE;
end
GET_ADDR_R : begin
if (r_RX_DV_OLD == 1'b0 &&
((din >= 8'h30 && din < 8'h3A) || // if 0-9
(din >= 8'h61 && din <= 8'h66) ) // if a-f
&& r_addr_byte < 'h4 )
begin
if (din >= 8'h30 && din < 8'h3A) begin // if 0-9
r_addr_rd = r_addr_rd * 'd10 + din - 'h30 ;
r_addr_byte <= r_addr_byte + 1;
end
end
else if
(r_RX_DV_OLD == 1'b0 &&
((din >= 8'h30 && din < 8'h3A) || // if 0-9
(din >= 8'h61 && din <= 8'h66) ) // if a-f
&& r_addr_byte == 'h4)
begin
if (din >= 8'h30 && din < 8'h3A) begin // if 0-9
r_addr_rd = r_addr_rd * 'd10 + din - 'h30 ;
r_next <= READ_MEM;
end
end
end
READ_MEM : begin
r_next <= IDLE;
r_addr_byte <= 0;
end
// wrinting in register memory
GET_ADDR_W_REG : begin
if (r_RX_DV_OLD == 1'b0 &&
((din >= 8'h30 && din < 8'h3A) || // if 0-9
(din >= 8'h61 && din <= 8'h66) ) // if a-f
&& r_addr_byte < 'h1 )
begin
if (din >= 8'h30 && din < 8'h3A) begin // if 0-9
r_addr_wr_reg = r_addr_wr_reg * 'h10 + din - 'h30 ;
r_addr_byte <= r_addr_byte + 1;
end
else if (din >= 8'h61 && din <= 8'h66) begin // if a-f
r_addr_wr_reg = r_addr_wr_reg * 'h10 + din - 'h57 ;
r_value_byte <= r_value_byte + 1;
end
end
else if
(r_RX_DV_OLD == 1'b0 &&
((din >= 8'h30 && din < 8'h3A) || // if 0-9
(din >= 8'h61 && din <= 8'h66) ) // if a-f
&& r_addr_byte == 'h1)
begin
if (din >= 8'h30 && din < 8'h3A) begin // if 0-9
r_addr_wr_reg = r_addr_wr_reg * 'h10 + din - 'h30 ;
r_value_byte <= 'b0;
r_next <= GET_VALUE_W_REG;
end
else if (din >= 8'h61 && din <= 8'h66) begin // if a-f
r_addr_wr_reg = r_addr_wr_reg * 'h10 + din - 'h57 ;
r_value_byte <= 'b0;
r_next <= GET_VALUE_W_REG;
end
end
end
GET_VALUE_W_REG : begin
if (r_RX_DV_OLD == 1'b0 &&
((din >= 8'h30 && din < 8'h3A) || // if 0-9
(din >= 8'h61 && din <= 8'h66) ) // if a-f
&& r_value_byte < 'd6 )
begin
if (din >= 8'h30 && din < 8'h3A) begin // if 0-9
r_data_reg = r_data_reg * 'h10 + din - 'h30 ;
r_value_byte <= r_value_byte + 1;
end
else if (din >= 8'h61 && din <= 8'h66) begin // if a-f
r_data_reg = r_data_reg * 'h10 + din - 'h57 ;
r_value_byte <= r_value_byte + 1;
end
end
else if
(r_RX_DV_OLD == 1'b0 &&
((din >= 8'h30 && din < 8'h3A) || // if 0-9
(din >= 8'h61 && din <= 8'h66) ) // if a-f
&& r_value_byte == 'd6)
begin
if (din >= 8'h30 && din < 8'h3A) begin // if 0-9
r_data_reg = r_data_reg * 'h10 + din - 'h30 ;
r_we_reg <= 1'b1;
r_next <= WRITE_MEM_REG;
end
else if (din >= 8'h61 && din <= 8'h66) begin // if a-f
r_data_reg = r_data_reg * 'h10 + din - 'h57 ;
r_we_reg <= 1'b1;
r_next <= WRITE_MEM_REG;
end
end
end
WRITE_MEM_REG : begin
r_we_reg <= 1'b0;
r_addr_wr_reg <= 1'b0;
r_value_byte <= 1'b0;
r_next <= IDLE;
end
default: r_next <= IDLE; // on error
endcase
r_RX_DV <= 'b0;
end
end
end
//-------------------- assignning combionational logic----------------------------
assign write = r_write;
assign addr_wr = r_addr_wr ;
assign data_wr = r_data_wr ;
assign addr_rd = r_addr_rd ;
assign o_state = r_state;
assign o_byte = (r_state == 'h1 || r_state == 'h4 ) ? r_addr_byte : r_value_byte;
assign o_addr_wr_reg = r_addr_wr_reg;
assign o_data_reg = r_data_reg;
assign o_we_reg = r_we_reg;
endmodule
com_to_mem_module.v
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// This module is based on Top module: com_to_mem_top.v
// recive comand, addres and data by
// UART and write information in Block RAM
//`include "clock_divider_param.v"
//`include "clock_enable_param.v"
//`include "7segment_v2.v"
//`include "com_to_mem_FSM.v"
//`include "UART_Loopback_module.v"
module com_to_mem #( parameter
WAIT = 1,
WAIT_WIDTH = 2,
ADDR_WIDTH = 17,
DATA_WIDTH = 8,
DEPTH = 76_800
)(
input clk,
input sw,
input i_enable,
// input [DATA_WIDTH-1:0] i_data_rd,
input RsRx, // UART RX Data
output RsTx, // UART TX Data
output [6:0] seg,
output [3:0] an,
// output dp,
output [ADDR_WIDTH-1:0] o_addr_wr,
output [ADDR_WIDTH-1:0] o_addr_rd,
output [DATA_WIDTH-1:0] o_data_wr,
output o_write ,
output [6:0] o_addr_wr_reg,
output [24:0] o_data_reg,
output o_we_reg
);
wire clk10k;
wire [7:0] w_dout;
wire w_RX_DV;
wire w_TX_Done;
wire [3:0] w_state;
wire [3:0] w_byte;
//------ instatiated modules ---------------------------
com_to_mem_FSM #(
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.DEPTH(DEPTH)
) FSM1(
.clk(clk),
.i_enable(i_enable),
.din(w_dout),
.TX_Done(w_TX_Done),
.i_RX_DV(w_RX_DV),
.addr_wr(o_addr_wr),
.addr_rd(o_addr_rd),
.data_wr(o_data_wr),
.write(o_write),
.o_state(w_state),
.o_byte(w_byte),
.o_addr_wr_reg(o_addr_wr_reg),
.o_data_reg(o_data_reg),
.o_we_reg(o_we_reg)
);
bin_7segment bin_7segment1(
.clk(clk10k),
.sw({w_state, w_byte, w_dout}),
.seg(seg),
.an(an),
.dp());
UART_Loopback_module #(
.DATA_WIDTH('d8)
) UART_Loopback_module1
( .clk(clk),
.loopback(sw),
.RsRx(RsRx),
.RsTx(RsTx),
.dout(w_dout),
.o_TX_Done(w_TX_Done),
.o_RX_DV(w_RX_DV));
clock_divider #(
.DIVIDER(1_000),
.WIDTH(24)
) clock_divider7seg (
.clk(clk),
.clk_out(clk10k)
);
endmodule
com_to_mem_tb.v
+487
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@@ -0,0 +1,487 @@
// This file is Test Bench for UART to memory module
// its simulates UART comands sent to FPGA to
// write in memmory address value.
// 100MHz clock on Basys3 -> 10ns period
// 50% duty cycle 5ns HIGH and 5ns LOW
//`timescale [time unit] / [time precision]
`timescale 10 ns / 1ns
`include "UART_Loopback_module.v"
`include "UART_TX.v"
`include "UART_RX.v"
`include "clock_divider_param.v"
`include "clock_enable_param.v"
`include "bram.v"
`include "7segment.v"
`include "com_to_mem_FSM_hex.v"
`include "com_to_mem_top.v"
module com_to_mem_tb();
reg clk = 1'b1;
reg RsRx; // UART RX Data
wire RsTx; // UART TX Data
wire [15:0] led;
wire [6:0] seg;
wire [3:0] an;
reg sw=1'b1;
//wire dp;
// 50% duty cycle clock
always #0.5 clk <= ~clk;
initial begin
// starting UART transition
// h70 -> p
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
// h30 -> 0
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h30 -> 0
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h30 -> 0
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h35 -> 5
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h35 -> 5
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h32 -> 2
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h35 -> 5
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h35 -> 5
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#10_000;
// h72 -> r
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
// h30 -> 0
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h30 -> 0
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h30 -> 0
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h35 -> 5
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h35 -> 5
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#10_000;
// h70 -> p
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
// h30 -> 0
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h30 -> 0
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h30 -> 0
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h35 -> 5
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h35 -> 5
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h32 -> 2
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h35 -> 5
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h35 -> 5
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#10_000;
// h72 -> r
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
// h30 -> 0
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h30 -> 0
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h30 -> 0
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h35 -> 5
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h35 -> 5
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#10_000;
$display(" ");
$display("Use this command to open timing diagram:");
$display("gtkwave -f wave.vcd");
$display("----------------------------------------------");
$finish();
end
initial
begin
$display(" ");
$display("----------------------------------------------");
$display(" Starting Testbench...");
$dumpfile("wave.vcd");
$dumpvars(0);
end
top Test_Unit(
.clk(clk),
.sw(sw),
.RsRx(RsRx),
.RsTx(RsTx),
.led(led),
.seg(seg),
.an(an)//,
// .dp(dp)
);
endmodule
debounce_switch.v
+24
View File
@@ -0,0 +1,24 @@
module debounce_switch(
input clk,
input i_switch,
output o_switch);
parameter c_debounce_limit=250000;// 10ms at 25MHz
reg r_state=1'b0;
reg [17:0] r_count = 0;
always@(posedge clk)begin
if (i_switch != r_state && r_count < c_debounce_limit)
r_count <= r_count +1; //counter
else if (r_count == c_debounce_limit)begin
r_count <=0;
r_state <= i_switch;
end
else
r_count<=0;
end
assign o_switch=r_state;
endmodule
horizontal_counter.v
+73
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@@ -0,0 +1,73 @@
module horizontal_counter #(
parameter
HSYNC_CLKS = 800,
HSYNC_DISPLAY = 640,
HSYNC_PULSE = 96,
HSYNC_FRONT_PORCH = 16,
HSYNC_BACK_PORCH = 48
)(
input clk,
output o_Hsync,
output o_h_display,
output [9:0] o_h_pixel
);
//----------Internal registers, constants and wariables-----
reg hsync_reg = 1'b1;
reg [9:0] counter_reg = 'h0;
reg [9:0] counter_pixel_reg = 'h0;
reg [2:0] r_state=HS_FRONT_PORCH, r_next=HS_FRONT_PORCH;
localparam [2:0] HS_FRONT_PORCH = 'h0,
HS_PULSE = 'h1,
HS_BACK_PORCH = 'h2,
HS_DISPLAY = 'h3;
//---------state register sequential always block-----------
always @(posedge clk ) begin
r_state <= r_next;
end
//----next state & outputs, combinational always block------
always@(posedge clk) begin
counter_reg <= counter_reg + 1;
case (r_state)
HS_FRONT_PORCH: begin
hsync_reg <= 1'b1;
if(counter_reg == HSYNC_FRONT_PORCH - 2)
r_next <= HS_PULSE;
end
HS_PULSE:begin
hsync_reg <= 1'b0;
if(counter_reg == HSYNC_FRONT_PORCH +
HSYNC_PULSE - 2)
r_next <= HS_BACK_PORCH;
end
HS_BACK_PORCH:begin
hsync_reg <= 1'b1;
if(counter_reg == HSYNC_FRONT_PORCH +
HSYNC_PULSE +
HSYNC_BACK_PORCH - 2) begin
r_next <= HS_DISPLAY;
counter_pixel_reg <= 'h0;
end
end
HS_DISPLAY:begin
hsync_reg <= 1'b1;
counter_pixel_reg <= counter_pixel_reg + 1;
if(counter_reg == HSYNC_FRONT_PORCH +
HSYNC_PULSE +
HSYNC_BACK_PORCH +
HSYNC_DISPLAY - 1) begin
r_next <= HS_FRONT_PORCH;
counter_reg <= 'h0;
end
end
endcase
end
assign o_Hsync = hsync_reg;
assign o_h_display = (counter_pixel_reg >= 1 && counter_pixel_reg <= HSYNC_DISPLAY) ? 1'b1 : 1'b0 ;
assign o_h_pixel = counter_pixel_reg - 1 ;
endmodule
pattern_gen.v
+150
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@@ -0,0 +1,150 @@
// This module generates color patherns and rwite them in
// BlockRAM memory
//
module pattern_gen #( parameter
LINES = 480,
COLUMNS = 640,
DEPTH = 76_800, //307_200, //
ADDR_WIDTH = 17,
DATA_WIDTH = 12,
SPEED = 2,
SIZE = 2
)(
input clk,
input i_enable,
// input sw,
output [ADDR_WIDTH-1:0] o_addr,
output [DATA_WIDTH-1:0] o_data,
output o_write);
//-------------Internal Constants---------------------------
//reg [ADDR_WIDTH-1:0] counter_reg = 'b0;
reg [31:0] speed_counter_reg = 'b0;
//reg [DATA_WIDTH-1:0] color_reg = 'b0;
reg [3:0] red_reg = 'b0;
reg [3:0] blue_reg = 'b0;
reg [3:0] green_reg = 'b0;
reg [8:0] line_reg = 'b0;
reg [9:0] column_reg = 'b0;
reg write_reg=1'b0;
/*
localparam [SIZE-1:0] GREEN = 'h0,
RED = 'h1,
BLUE = 'h2;
reg [SIZE-1:0] state_reg=GREEN, next_reg=GREEN;
//---------state register sequential always block-----------
always @(posedge clk ) begin
if (i_enable) begin
state_reg <= next_reg;
end
end
*/
//----next state & outputs, combinational always block------
always @(posedge clk) begin
speed_counter_reg <= speed_counter_reg + 1;
if(speed_counter_reg == SPEED) begin
write_reg <= 1'b1;
speed_counter_reg <= 0;
if(i_enable) begin
// counter_reg <= counter_reg + 1;
if(column_reg < COLUMNS-1) begin
column_reg <= column_reg + 1 ;
end
else begin
column_reg <= 0;
if (line_reg< LINES -1 ) begin
line_reg <= line_reg + 1;
end
else begin
line_reg <= 0;
end
end
/*
if (line_reg < 239 ) begin
green_reg <= 4'b1111;
end
else begin
green_reg <= 4'b0000;
end
*/
/*
if (column_reg < 319 || column_reg == 639) begin
red_reg <= 4'b1111;
end
else begin
red_reg <= 4'b0000;
end
*/
/*
case (state_reg)
GREEN : begin
color_reg <= 12'b111100000000;
if(counter_reg == DEPTH - 1) begin
next_reg <= RED;
counter_reg <= 'b0;
end
end
RED : begin
color_reg <= 12'b000011110000;
if(counter_reg == DEPTH - 1 ) begin
next_reg <= BLUE;
counter_reg <= 'b0;
end
end
BLUE : begin
color_reg <= 12'b000000001111;
if(counter_reg == DEPTH - 1) begin
next_reg <= GREEN;
counter_reg <= 'b0;
end
end
default: begin
next_reg <= GREEN ;
counter_reg <= 'b0;
end
endcase
*/
end
end
else if (i_enable) write_reg <= 1'b0;
end
always@* begin
if (line_reg < 239 ) begin
green_reg <= 4'b1111;
end
else begin
green_reg <= 4'b0000;
end
if (column_reg > 319 ) begin
red_reg <= 4'b1111;
end
else begin
red_reg <= 4'b0000;
end
end
assign o_addr = (line_reg[8:1] * COLUMNS/2) + column_reg [9:1] ;
assign o_data = {green_reg, red_reg , blue_reg};
//assign o_write = sw ? write_reg : 1'b0 ; // remowing switch
assign o_write = write_reg;
endmodule
pattern_gen_tb.v
+71
View File
@@ -0,0 +1,71 @@
// 100MHz clock on Basys3 -> 10ns period
// 50% duty cycle 5ns HIGH and 5ns LOW
//`timescale [time unit] / [time precision]
`timescale 10 ns / 1ns
`include "pattern_gen.v"
`include "clock_enable_param.v"
module pattern_gen_tb#( parameter
ADDR_WIDTH = 17,
DATA_WIDTH = 8
) ();
// for clock_divider
reg clk = 1'b0;
wire enable;
wire [ADDR_WIDTH-1:0] addr ;
wire [DATA_WIDTH-1:0] data ;
// generate clk
always #0.5 clk <= ~clk;
initial
begin
#76_800;
#76_800;
#76_800;
#76_800;
#76_800;
#76_800;
#76_800;
#76_800;
#76_800;
#76_800;
$display(" ");
$display("Use this command to open timing diagram:");
$display("gtkwave -f wave.vcd");
$display("----------------------------------------------");
$finish();
end
initial
begin
$display(" ");
$display("----------------------------------------------");
$display(" Starting Testbench...");
$dumpfile("wave.vcd");
$dumpvars(0);
end
clock_enable_param #(
.WAIT(1),
.WIDTH(2)
) clock_enable1 (
.clk(clk),
.enable(enable));
address_gen #(
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH)
) test_unit (
.clk(clk),
.i_enable(enable),
.o_addr(addr),
.o_data(data));
endmodule
top.v
+195
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@@ -0,0 +1,195 @@
// TOP module
//
//
// `include "clock_divider_param.v"
// `include "clock_enable_param.v"
// `include "blockram.v"
// `include "pattern_gen.v"
// `include "vga_module.v"
// `include "horizontal_counter.v"
// `include "vertical_counter.v"
module top #( parameter
//pattern generator paremater
SPEED = 300,
//enable signal parameters
WAIT = 1,
WAIT_WIDTH = 2,
//memory parameters
ADDR_WIDTH = 17, // 19, //
DATA_WIDTH = 12,
DEPTH = 76_800, // 307_200,//
//VGA parameters
HSYNC_CLKS = 800,
HSYNC_DISPLAY = 640,
HSYNC_PULSE = 96,
HSYNC_FRONT_PORCH = 16,
HSYNC_BACK_PORCH = 48,
VSYNC_LINES = 521,
VSYNC_DISPLAY = 480,
VSYNC_PULSE = 2,
VSYNC_FRONT_PORCH = 10,
VSYNC_BACK_PORCH = 29
)(
input clk,
output [11:0] led,
output [1:0] ledc, // led camera configuration indicator
//VGA inputs outputs
output [3:0] vgaRed,
output [3:0] vgaBlue,
output [3:0] vgaGreen,
output Hsync,
output Vsync,
input [2:0] sw,
//UART
input RsRx, // UART RX Data
output RsTx, // UART TX Data
// 7 segment
output [6:0] seg,
output [3:0] an
);
//------internal wires and registers--------
wire w_enable;
wire pixel_clk;
wire clk50;
wire w_write;
wire [ADDR_WIDTH-1:0] w_addr_wr;
wire [DATA_WIDTH-1:0] w_data_wr;
wire [ADDR_WIDTH-1:0] w_com_addr_wr;
wire [DATA_WIDTH-1:0] w_com_data_wr;
wire w_com_write;
wire [ADDR_WIDTH-1:0] w_com_addr_rd;
// wire [ADDR_WIDTH-1:0] w_addrb;
wire [ADDR_WIDTH-1:0] w_addr_rd;
wire [DATA_WIDTH-1:0] w_data_rd;
//-----sub modules--------------------------
clock_enable_param #(
.WAIT(WAIT),
.WIDTH(WAIT_WIDTH)
) clock_enable1 (
.clk(clk),
.enable(w_enable)
);
clock_divider #(
.DIVIDER(2),
.WIDTH(3)
) clk25mhz_gen (
.clk(clk),
.clk_out(pixel_clk)
);
pattern_gen #(
.DEPTH(DEPTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.SPEED(SPEED)
) pattern_gen1 (
.clk(clk),
// .sw(sw[1]),
.i_enable(w_enable),
.o_addr(w_addr_wr),
.o_data(w_data_wr),
.o_write(w_write)
);
rams_tdp_rf_rf #(
.DEPTH(DEPTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH))
bram3(
// -------------------------PORT A
.clka(clk),
.ena( 1'b1 /*w_enable*/),
.wea( w_wea_bram ),
.addra( w_addra_bram ),
.dia( w_dia_bram ),
.doa( w_doa_bram ),
//---------------------------PORT B
.clkb(clk),
.addrb( w_addr_rd ),
.enb(w_enable),
//.web(),
//.dib(),
.dob(w_data_rd));
vga_module #(
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.DEPTH(DEPTH),
.HSYNC_CLKS(HSYNC_CLKS),
.HSYNC_DISPLAY(HSYNC_DISPLAY),
.HSYNC_PULSE(HSYNC_PULSE),
.HSYNC_FRONT_PORCH(HSYNC_FRONT_PORCH),
.HSYNC_BACK_PORCH(HSYNC_BACK_PORCH),
.VSYNC_LINES(VSYNC_LINES) ,
.VSYNC_DISPLAY(VSYNC_DISPLAY) ,
.VSYNC_PULSE(VSYNC_PULSE) ,
.VSYNC_FRONT_PORCH(VSYNC_FRONT_PORCH) ,
.VSYNC_BACK_PORCH(VSYNC_BACK_PORCH)
) vga_module1 (
.clk(pixel_clk),
.o_vgaRed(vgaRed),
.o_vgaBlue(vgaBlue),
.o_vgaGreen(vgaGreen),
.o_Hsync(Hsync),
.o_Vsync(Vsync),
.o_display(),
.o_addr_rd(w_addr_rd),
.o_data_rd(w_data_rd)
);
com_to_mem #(
.WAIT(WAIT),
.WAIT_WIDTH(WAIT_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.DEPTH(DEPTH)
) com_to_mem1 (
.clk(clk),
.sw(sw[0]),
//.i_data_rd(w_doa_bram),
.i_enable(w_enable),
.o_addr_wr(w_com_addr_wr),
.o_addr_rd(w_com_addr_rd),
.o_data_wr(w_com_data_wr),
.o_write(w_com_write),
.RsRx(RsRx), // UART RX Data
.RsTx(RsTx), // UART TX Data
.seg(seg),
.an(an),
.o_addr_wr_reg(w_addr_com_wr_reg),
.o_data_reg(w_data_com_reg),
.o_we_reg(w_we_com_reg)
);
// debounce_switch debounce_switch_reset(
// .clk(clk),
// .i_switch(btnU),
// .o_switch(w_reset_default)
// );
endmodule
top_tb.v
+579
View File
@@ -0,0 +1,579 @@
// This file is Test Bench for top_vga_mem module
//
//
// 100MHz clock on Basys3 -> 10ns period
// 50% duty cycle 5ns HIGH and 5ns LOW
//`timescale [time unit] / [time precision]
`timescale 10 ns / 1ns
//sub modules
`include "clock_divider_param.v"
`include "clock_enable_param.v"
`include "blockram.v"
`include "pattern_gen.v"
`include "vga_module.v"
`include "horizontal_counter.v"
`include "vertical_counter.v"
`include "UART_Loopback_module.v"
`include "UART_TX.v"
`include "UART_RX.v"
`include "7segment.v"
`include "com_to_mem_FSM_hex.v"
`include "com_to_mem_module.v"
`include "debounce_switch.v"
//top module
`include "top.v"
module top_vga_mem_tb#( parameter
WAIT = 1,
WAIT_WIDTH = 2,
SPEED = 2,
//memory parameters
ADDR_WIDTH = 17, //19, //
DATA_WIDTH = 12,
DEPTH = 307_200//76_800, //
)();
reg clk = 1'b0;
reg pclk = 1'b0;
reg hs = 1'b0;
reg vs = 1'b0;
// 50% duty cycle clock
always #0.5 clk <= ~clk;
always #2 pclk <= ~pclk;
always #100 hs <= 1;
always #102 hs <= 0;
always #200 vs <= 1;
always #202 vs <= 0;
reg RsRx;
wire RsTx;
top_vga_mem #(
.SPEED(SPEED),
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.DEPTH(DEPTH)
)Test_Unit(
.clk(clk),
.RsRx(RsRx),
.RsTx(RsTx),
.sw(3'b101),
.ov7670_cam1_pclk(pclk),
.ov7670_cam2_pclk(pclk),
.ov7670_cam1_vs(vs),
.ov7670_cam1_hs(hs),
.ov7670_cam2_vs(vs),
.ov7670_cam2_hs(hs),
.im_p(9'b00_01_01_000)
);
initial begin
// starting UART transition
// h70 -> P
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
// h30 -> 0
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h32 -> 2
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h30 -> 0
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h30 -> 0
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h30 -> 0
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h30 -> 0
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h30 -> 0
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h63 -> c
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
// h38 -> 8
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#10_000;
// h72 -> r
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
// h30 -> 0
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h30 -> 0
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h30 -> 0
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h35 -> 5
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h35 -> 5
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#10_000;
// h70 -> p
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
// h30 -> 0
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h30 -> 0
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h30 -> 0
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h35 -> 5
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h35 -> 5
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h32 -> 2
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h35 -> 5
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h35 -> 5
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#10_000;
// h72 -> r
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
// h30 -> 0
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h30 -> 0
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h30 -> 0
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h35 -> 5
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
// h35 -> 5
#9000;
#0 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 1;
#868 RsRx = 1;
#868 RsRx = 0;
#868 RsRx = 0;
#868 RsRx = 1;
#10_000;
end
initial begin
#000_001;
$display("*");
#030_000;
$display("*");
#030_000;
$display("*");
#030_000;
$display("*");
#030_000;
$display("*");
#030_000;
$display("*");
#030_000;
$display("*");
#030_000;
$display("*");
#030_000;
$display("*");
#030_000;
$display("*");
#030_000;
$display("*");
#030_000;
$display("*");
#030_000;
$display("*");
#030_000;
$display("*");
#030_000;
$display("*");
#030_000;
$display("*");
#030_000;
$display("*");
#030_000;
$display("*");
#030_000;
$display("*");
#030_000;
$display("*");
$display(" ");
$display("Use this command to open timing diagram:");
$display("gtkwave -f wave.vcd");
$display("----------------------------------------------");
$finish();
end
initial
begin
$display(" ");
$display("----------------------------------------------");
$display(" Starting Testbench...");
$dumpfile("wave.vcd");
$dumpvars(0);
end
endmodule
vertical_counter.v
+73
View File
@@ -0,0 +1,73 @@
module vertical_counter #(
parameter
VSYNC_LINES = 521,
VSYNC_DISPLAY = 480,
VSYNC_PULSE = 2,
VSYNC_FRONT_PORCH = 10,
VSYNC_BACK_PORCH = 29
)(
//input clk,
input i_Hsync,
output o_Vsync,
output o_v_display,
output [8:0] o_v_line
);
//----------Internal registers, constants and wariables-----
reg vsync_reg = 1'b1;
reg [9:0] counter_reg = 'h0;
reg [8:0] counter_line_reg = 'h0;
reg [2:0] r_state=VS_FRONT_PORCH, r_next=VS_FRONT_PORCH;
localparam [2:0] VS_FRONT_PORCH = 'h0,
VS_PULSE = 'h1,
VS_BACK_PORCH = 'h2,
VS_DISPLAY = 'h3;
//---------state register sequential always block-----------
always @(posedge i_Hsync ) begin
r_state <= r_next;
end
//----next state & outputs, combinational always block------
always@(posedge i_Hsync) begin
counter_reg <= counter_reg + 1;
case (r_state)
VS_FRONT_PORCH: begin
vsync_reg <= 1'b1;
if(counter_reg == VSYNC_FRONT_PORCH - 2)
r_next <= VS_PULSE;
end
VS_PULSE:begin
vsync_reg <= 1'b0;
if(counter_reg == VSYNC_FRONT_PORCH +
VSYNC_PULSE - 2)
r_next <= VS_BACK_PORCH;
end
VS_BACK_PORCH:begin
vsync_reg <= 1'b1;
if(counter_reg == VSYNC_FRONT_PORCH +
VSYNC_PULSE +
VSYNC_BACK_PORCH - 2) begin
r_next <= VS_DISPLAY;
counter_line_reg <= 'h0;
end
end
VS_DISPLAY:begin
vsync_reg <= 1'b1;
counter_line_reg <= counter_line_reg + 1;
if(counter_reg == VSYNC_FRONT_PORCH +
VSYNC_PULSE +
VSYNC_BACK_PORCH +
VSYNC_DISPLAY - 1) begin
r_next <= VS_FRONT_PORCH;
counter_reg <= 'h0;
end
end
endcase
end
assign o_Vsync = vsync_reg;
assign o_v_display = (counter_line_reg >= 1 && counter_line_reg <= VSYNC_DISPLAY) ? 1'b1 : 1'b0 ;
assign o_v_line = counter_line_reg - 1 ;
endmodule
vga_module.v
+76
View File
@@ -0,0 +1,76 @@
module vga_module#(
parameter
ADDR_WIDTH = 17,
DATA_WIDTH = 12,
DEPTH = 76_800, // 307_200,//
HSYNC_CLKS = 800,
HSYNC_DISPLAY = 640,
HSYNC_PULSE = 96,
HSYNC_FRONT_PORCH = 16,
HSYNC_BACK_PORCH = 48,
VSYNC_LINES = 521,
VSYNC_DISPLAY = 480,
VSYNC_PULSE = 2,
VSYNC_FRONT_PORCH = 10,
VSYNC_BACK_PORCH = 29
)(
input clk,
output [3:0] o_vgaRed,
output [3:0] o_vgaBlue,
output [3:0] o_vgaGreen,
output o_Hsync,
output o_Vsync,
output o_display,
output [ADDR_WIDTH-1:0] o_addr_rd,
input [DATA_WIDTH-1:0] o_data_rd
);
//-------Internal registers and wires--------------
wire w_v_display;
wire w_h_display;
wire [9:0] pixel;
wire [8:0] line;
//-------sub modules-------------------------------
horizontal_counter #(
.HSYNC_CLKS(HSYNC_CLKS) ,
.HSYNC_DISPLAY(HSYNC_DISPLAY) ,
.HSYNC_PULSE(HSYNC_PULSE) ,
.HSYNC_FRONT_PORCH(HSYNC_FRONT_PORCH) ,
.HSYNC_BACK_PORCH(HSYNC_BACK_PORCH)
) horizontal_counter1 (
.clk(clk),
.o_Hsync(o_Hsync),
.o_h_display(w_h_display),
.o_h_pixel(pixel)
);
vertical_counter #(
.VSYNC_LINES(VSYNC_LINES) ,
.VSYNC_DISPLAY(VSYNC_DISPLAY) ,
.VSYNC_PULSE(VSYNC_PULSE) ,
.VSYNC_FRONT_PORCH(VSYNC_FRONT_PORCH) ,
.VSYNC_BACK_PORCH(VSYNC_BACK_PORCH)
) vertical_counter1 (
//.clk(clk),
.i_Hsync(o_Hsync),
.o_Vsync(o_Vsync),
.o_v_display(w_v_display),
.o_v_line(line)
);
assign o_display = (w_v_display && w_h_display) ;
assign o_vgaRed = o_display ? o_data_rd[11:8] : 4'h0;
assign o_vgaBlue = o_display ? o_data_rd[3:0] : 4'h0;
assign o_vgaGreen = o_display ? o_data_rd[7:4] : 4'h0;
/*
assign o_addr_rd = (((line*HSYNC_DISPLAY) + pixel + 1) == HSYNC_DISPLAY * VSYNC_DISPLAY ) ?
'h0 : ((line[8:1]) * HSYNC_DISPLAY/2 ) + pixel[9:1] + 1 ; // get next pixel
*/
assign o_addr_rd =
((line[8:1]) * 'd320 ) + pixel[9:1];// + 1;
endmodule