Add Matlab files

Matlab/convert.m

@@ -0,0 +1,70 @@
+%% converting decimal to binary floting point
+%
+%   | Sign | Exponent  | Mantissa |  
+%   | 1bit |   8bits   |  18bits  |
+%
+%   2^0 => Exponent = 'd127 = 'h7f
+%
+%   Mantissa = [ ( 1-2^(-126) ) ; 0.5 ]
+%   
+%
+clear all;
+x = 4/320 ; % number to convert
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+exponent = 127;
+%
+% calculating exponent and mantissa
+%
+x_new = abs(x);
+while (x_new >= 1 && exponent <255 && exponent >0)
+   x_new = x_new / 2;
+   exponent = exponent + 1;
+end
+while (x_new < 0.5 && exponent <255 && exponent >0) 
+   x_new = x_new * 2;
+   exponent = exponent -1;
+end
+% covertin x and exponent to fixed point number
+disp( ' ' )
+print = ['Converting decimal number ' , num2str(x) , ' to floting point number:'];
+disp( print );
+if (x < 0) 
+    print = ['-'];
+else
+    print = [' '];
+end 
+print = [ '           ' , print , num2str(x_new) , '*2^' ,  num2str(exponent - 127)];
+disp( print );
+% if number are out of boundaries pront overflow
+if (exponent == 255 || exponent == 0)
+    disp( ' ' );
+    disp( '************overflow*************' );
+    disp( ' ' );
+end
+%% Convering to binary
+% Sign
+if (x < 0 ) 
+    string_bin = ['1'];
+else
+    string_bin = ['0'];
+end
+% Exponent
+exp_ufi = ufi(exponent,8,0);
+temp = [exp_ufi.bin];
+for n=7:-1:0
+    string_bin = [string_bin, temp(end-n)];
+end
+% Mantissa
+x_ufi = ufi(x_new,19,18);
+temp = [x_ufi.bin];
+for n=18:-1:0
+    string_bin = [string_bin, temp(end-n)];
+end
+string_hex = dec2hex(bin2dec(string_bin),7);
+%% printing out result
+disp( ' ' );
+print = [ ' 27`b_ = ' , string_bin];
+disp( print );
+print = [ ' 27`h_ = ' , string_hex];
+disp( print );
+disp( ' ' );

Matlab/mandelbrot.m

@@ -0,0 +1,36 @@
+%
+%
+% Clar figure 1 and workspace
+clear all
+%figure(1); clf;
+% Image size
+columns = 320;
+rows = 240;
+% Terminate after n cycles
+termination = 1000;
+
+x = linspace(-2, 2, columns); %[-2,1]
+y = linspace(-1.5, 1.5, rows); %[-1,1]
+%
+% make blank(white) matrix
+x_index = 1:length(x) ;
+y_index = 1:length(y) ;
+img = ones(length(y),length(x));
+
+for k=x_index
+    for j=y_index
+        z = 0;
+        n = 0;
+        c = x(k)+ y(j)*i ;%complex number
+        while (abs(z)<2 && n<termination)
+            z = z^2 + c;
+            n = n + 1;
+        end
+        img(j,k) = fix(log2(n));
+    end
+end
+
+imagesc(img)
+imwrite(img,'mandelbrot.jpeg','JPEG');
+
+

Matlab/mandelbrot_log.m

@@ -0,0 +1,32 @@
+%
+% Source:
+% http://people.ece.cornell.edu/land/courses/ece5760/LABS/s2019/lab3_mandelbrot.html
+%
+clear all
+figure(1); clf;
+
+termination = 100;
+x = linspace(-1.45, -1.3, 640); %[-2,1]
+y = linspace(-0.07, 0.07, 480); %[-1,1]
+
+x_index = 1:length(x) ;
+y_index = 1:length(y) ;
+img = zeros(length(y),length(x));
+
+
+for k=x_index
+    for j=y_index
+        z = 0;
+        n = 0;
+        c = x(k)+ y(j)*i ;%complex number
+        while (abs(z)<2 && n<termination)
+            z = z^2 + c;
+            n = n + 1;
+        end
+        img(j,k) = fix(log2(n));
+    end
+end
+
+imagesc(img)
+colormap(summer)
+

mux.v

@@ -1,27 +1,29 @@
-module mux #( parameter
+module mux #( 
-    DATA_WIDTH = 12, 
+    // parameter
-    SELECT_WIDTH = 4
+    // DATA_WIDTH = 12, 
+    // SELECT_WIDTH = 4
 )(
-    input [SELECT_WIDTH - 1 :0]     select,
+    input [3 :0]     select,
-    input [DATA_WIDTH - 1 :0]       d0,
+    input [11 :0]       d0,
-    input [DATA_WIDTH - 1 :0]       d1,
+    input [11 :0]       d1,
-    input [DATA_WIDTH - 1 :0]       d2,
+    input [11 :0]       d2,
-    input [DATA_WIDTH - 1 :0]       d3,
+    input [11 :0]       d3,
-    input [DATA_WIDTH - 1 :0]       d4,
+    input [11 :0]       d4,
-    input [DATA_WIDTH - 1 :0]       d5,
+    input [11 :0]       d5,
-    input [DATA_WIDTH - 1 :0]       d6,
+    input [11 :0]       d6,
-    input [DATA_WIDTH - 1 :0]       d7,
+    input [11 :0]       d7,
-    input [DATA_WIDTH - 1 :0]       d8,
+    input [11 :0]       d8,
-    input [DATA_WIDTH - 1 :0]       d9,
+    input [11 :0]       d9,
-    input [DATA_WIDTH - 1 :0]       d10,
+    input [11 :0]       d10,
-    input [DATA_WIDTH - 1 :0]       d11,
+    input [11 :0]       d11,
-    input [DATA_WIDTH - 1 :0]       d12,
+    input [11 :0]       d12,
-    input [DATA_WIDTH - 1 :0]       d13,
+    input [11 :0]       d13,
-    input [DATA_WIDTH - 1 :0]       d14,
+    input [11 :0]       d14,
-    output[DATA_WIDTH - 1 :0]      o_q  
+    input [11 :0]       d15,
+    output[11 :0]       o_q  
 );
 
-reg [DATA_WIDTH - 1 :0]      q ;
+reg [11 : 0]      q;
 
 always @*
 begin
@@ -41,7 +43,7 @@ begin
        'd12 : q <= d12;
        'd13 : q <= d13;
        'd14 : q <= d14;
-       default : q <= d0;
+       'd15 : q <= d15;
    endcase
 end
 

top.v

@@ -11,7 +11,7 @@ module top #( parameter
     //memory parameters
     ADDR_WIDTH = 13, // 
     DATA_WIDTH = 12, 
-    DEPTH =  5_120, // ( 320 * 16 ) 
+    DEPTH =  4_800, // ( 320 * 15 ) 
     //VGA parameters
     HSYNC_CLKS = 800,
     HSYNC_DISPLAY = 640,
@@ -74,6 +74,7 @@ wire [DATA_WIDTH-1:0] w_data_rd11;
 wire [DATA_WIDTH-1:0] w_data_rd12;
 wire [DATA_WIDTH-1:0] w_data_rd13;
 wire [DATA_WIDTH-1:0] w_data_rd14;
+wire [DATA_WIDTH-1:0] w_data_rd15;
 
 //-----sub modules--------------------------
 clock_enable_param #(
@@ -165,8 +166,9 @@ vga_module #(
 // );
 
 mux #(
-    .DATA_WIDTH(DATA_WIDTH), 
+    // .DATA_WIDTH(DATA_WIDTH), 
-    .SELECT_WIDTH('d4)) 
+    // .SELECT_WIDTH('d4)
+    ) 
 mux1(
     .select(w_vga_line_mux),
     .d0(w_data_rd0),
@@ -184,6 +186,7 @@ mux1(
     .d12(w_data_rd12),
     .d13(w_data_rd13),
     .d14(w_data_rd14),
+    .d15(w_data_rd15),
     .o_q(w_data_rd));
 
 
@@ -519,4 +522,25 @@ bram14(
     //.dib(),
     .dob(w_data_rd14));
 
+blockram #( 
+    .DEPTH(DEPTH),
+    .ADDR_WIDTH(ADDR_WIDTH), 
+    .DATA_WIDTH(DATA_WIDTH)) 
+bram15(
+    // -------------------------PORT A (write)
+    .clka(clk),
+    .ena(  1'b1  /*w_enable*/),
+    .wea( w_write ),
+    .addra( w_addr_wr ),
+    .dia( w_data_wr ),
+    .doa(   ),
+
+    //---------------------------PORT B (read)
+    .clkb(clk),
+    .addrb( w_addr_rd ),
+    .enb(w_enable),
+    //.web(),
+    //.dib(),
+    .dob(w_data_rd15));
+
 endmodule

vga_module.v

@@ -71,8 +71,9 @@ assign o_addr_rd = (((line*HSYNC_DISPLAY) + column + 1) == HSYNC_DISPLAY * VSYNC
                         'h0 : ((line[8:1]) * HSYNC_DISPLAY/2 ) + column[9:1] + 1 ;   // get next pixel
 */
 assign o_addr_rd =  
-                    ((line[4:1]) * 'd320 ) + column[9:1];// + 1;
+                    ((line[8:5]) * 'd320 ) + column[9:1];// + 1;
 
-assign o_line_mux = line[8:5];
+//assign o_line_mux = line[8:5];
+assign o_line_mux = line[4:1];
 
 endmodule