14 lines
314 B
Verilog
14 lines
314 B
Verilog
module effect_controler #( parameter
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d_width = 24 // data width
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)(
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// input clk,
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input [d_width-1: 0] i_l_data,
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input [d_width-1: 0] i_r_data,
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output [d_width-1: 0] o_l_data,
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output [d_width-1: 0] o_r_data
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);
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assign o_l_data = i_l_data;
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assign o_r_data = i_r_data;
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endmodule |