98 lines
3.4 KiB
Verilog
98 lines
3.4 KiB
Verilog
// TOP module
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//
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// Fs = audio sample frequency
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// I2S bitrate = (#bits/channel) x (#channels) x Fs
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// Ex: 24-bit stereo (2 channels)
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// I2S bitrate = 24 x 2 x Fs
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//
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// I2SxCLK source = PLLI2S output or ext. input (I2S_CKIN)
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// Fs = 48kHz, 96kHz or 192kHz
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// Fs = I2SxCLK / [(CF*2) * (2*I2SDIV+ODD)*8)]
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// CF = channel frame (24 bits)
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//
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module top #( parameter
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sclk_ws_ratio = 64, // number of sclk periods per word select period
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mclk_sclk_ratio = 4, // number of mclk periods per sclk period
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d_width = 24 // data width
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)(
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input clk,
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input btnC,
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output da_mclk,
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output ad_mclk,
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output da_sclk,
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output ad_sclk,
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output da_lrck,
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output ad_lrck,
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input ad_sdout,
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output da_sdin
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);
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//------internal wires and registers--------
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wire master_clk; // 11.29 MHz master clock
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wire serial_clk;
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wire word_select;
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wire reset_n;
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wire [d_width-1: 0] r_data_tx;
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wire [d_width-1: 0] l_data_tx;
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wire [d_width-1: 0] r_data_rx;
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wire [d_width-1: 0] l_data_rx;
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wire w_sd_tx; //internal wire
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//-----sub modules--------------------------
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//declare PLL to create 11.29 MHz master clock from 100 MHz system clock
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clk_wiz_0 m_clk(
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.clk_in1(clk),
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.clk_out1(master_clk)
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);
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//instantiate I2S Transceiver component
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i2s_transceiver #(
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.mclk_sclk_ratio(mclk_sclk_ratio), //number of mclk periods per sclk period
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.sclk_ws_ratio(sclk_ws_ratio), //number of sclk periods per word select period
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.d_width(d_width) //data width
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) i2s_transceiver (
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.reset_n(reset_n), //asynchronous active low reset
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.mclk(master_clk), //master clock
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.sclk(serial_clk), //serial clock (or bit clock)
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.ws(word_select), //word select (or left-right clock)
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.sd_rx(ad_sdout), //serial data transmit
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.sd_tx(w_sd_tx), //serial data receive
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.l_data_tx(l_data_tx), //left channel data to transmit
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.r_data_tx(r_data_tx), //right channel data to transmit
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.l_data_rx(l_data_rx), //left channel data received
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.r_data_rx(r_data_rx) //right channel data received
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);
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//passing data to effect controler
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effect_controler #(
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.d_width(d_width) //data width
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) effect_controler (
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// .clk(clk),
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.i_l_data(l_data_rx), //left channel data received
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.i_r_data(r_data_rx), //right channel data received
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.o_l_data(l_data_tx), //left channel data to transmit
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.o_r_data(r_data_tx) //right channel data to transmit
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);
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//debounce reset button
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debounce_switch debounce_switch_reset(
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.clk(clk),
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.i_switch(btnC),
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.o_switch(reset_n)
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);
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assign da_mclk = master_clk; //output master clock to ADC
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assign ad_mclk = master_clk; //output master clock to DAC
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assign da_sclk = serial_clk; //output serial clock (from I2S Transceiver) to ADC
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assign ad_sclk = serial_clk; //output serial clock (from I2S Transceiver) to DAC
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assign da_lrck = word_select; //output word select (from I2S Transceiver) to ADC
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assign ad_lrck = word_select; //output word select (from I2S Transceiver) to DAC
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assign da_sdin = w_sd_tx; //assign right channel received data to transmit (to playback out received data)
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endmodule |