43 lines
1.5 KiB
Verilog
43 lines
1.5 KiB
Verilog
module effect_module #( parameter
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d_width = 16 // data width
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)(
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input clk,
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input reset,
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input [1:0] sw, // effect control swiches
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input i_data_ready, // data ready to read
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input signed [d_width-1: 0] i_data, // data input form effect controler
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output o_read_enable, // enable data reading
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input i_read_done, // read done from effects controler
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output signed [d_width-1: 0] o_data, // data output form effect controler
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output o_data_valid
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);
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// Wires for cliping effect
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wire signed [d_width-1: 0] w_data_ce;
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wire w_read_enable_ce;
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wire w_data_valid_ce;
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assign o_data = w_data_ce;// ? w_data_ce : 'b0 ;
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assign o_read_enable = w_read_enable_ce;//(i_data_ready & w_data_valid_ce ) ? w_read_enable_ce : 0 ;
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assign o_data_valid = w_data_valid_ce;//(i_data_ready & w_data_valid_ce ) ? w_data_valid_ce : 0 ;
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// clipping effect
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clipping_effect #(
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.data_width(d_width) // data width
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) clipping_effect (
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.clk(clk),
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.reset(reset),
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.i_treshhold(16'h00f0),
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.i_data(i_data),
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.i_read_done(i_data_ready),
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.o_data(w_data_ce),
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.o_read_enable(w_read_enable_ce),
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.o_data_valid(w_data_valid_ce),
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.i_data_ready(i_data_ready)
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);
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endmodule |