52 lines
911 B
Verilog
52 lines
911 B
Verilog
// This file is Test Bench for top module
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//
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//
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// 100MHz clock on Basys3 -> 10ns period
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// 50% duty cycle 5ns HIGH and 5ns LOW
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//`timescale [time unit] / [time precision]
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`timescale 10 ns / 1ns
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//sub modules
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`include "clock_divider_param.v"
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`include "clock_enable_param.v"
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`include "debounce_switch.v"
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//top module
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`include "top.v"
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module top_tb();
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reg clk = 1'b0;
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// 50% duty cycle clock
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always #0.5 clk <= ~clk;
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top UUT(
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.clk(clk)
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);
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initial begin
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#030_000;
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$display("*");
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$display(" ");
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$display("Use this command to open timing diagram:");
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$display("gtkwave -f wave.vcd");
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$display("----------------------------------------------");
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$finish();
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end
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initial
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begin
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$display(" ");
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$display("----------------------------------------------");
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$display(" Starting Testbench...");
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$dumpfile("wave.vcd");
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$dumpvars(0);
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end
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endmodule |