95 lines
2.0 KiB
Verilog
95 lines
2.0 KiB
Verilog
// This file is Test Bench for clipping module
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//
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//
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// 100MHz clock on Basys3 -> 10ns period
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// 50% duty cycle 5ns HIGH and 5ns LOW
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//`timescale [time unit] / [time precision]
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`timescale 10 ns / 1ns
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//sub modules
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`include "clipping.v"
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`include "no_effect.v"
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//top module
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`include "effect_module.v"
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module effect_tb#( parameter
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data_width = 16 // data width
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)();
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reg clk = 1'b0;
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reg signed [data_width-1 : 0] i_data = 'b0;
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reg i_read_done = 0;
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reg i_data_ready = 0;
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reg [1 : 0] sw = 2'b01;
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// 50% duty cycle clock
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always #0.5 clk <= ~clk;
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//Effect module contains all individual effects
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effect_module #(
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.d_width(data_width) // data width
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) effect_module (
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.clk(clk),
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.reset(1'b0),
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.sw(sw), // effect control swiches
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.i_treshhold(14'h0ff),
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.i_data_ready(i_data_ready), // data ready to read
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.i_read_done(i_read_done), // read done from effects controler
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.i_data(i_data), // data input form effect controler
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.o_read_enable(), // enable data reading
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.o_data_valid(),
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.o_data_sw0(),
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.o_data_sw1()
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);
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initial begin
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#030;
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i_data = 'haaa;
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#005;
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i_data_ready = 1;
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#005;
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i_data = 'h0fa;
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i_data_ready = 0;
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#002;
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i_read_done = 1;
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#001;
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i_read_done = 0;
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#005;
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i_data = -16'd3000;
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#002;
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i_read_done = 1;
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#001;
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i_read_done = 0;
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#005;
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i_data = 852;
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#002;
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i_read_done = 1;
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#001;
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i_read_done = 0;
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end
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initial begin
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#030_000;
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$display("*");
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$display(" ");
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$display("Use this command to open timing diagram:");
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$display("gtkwave -f wave.vcd");
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$display("----------------------------------------------");
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$finish();
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end
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initial
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begin
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$display(" ");
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$display("----------------------------------------------");
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$display(" Starting Testbench...");
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$dumpfile("wave.vcd");
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$dumpvars(0);
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end
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endmodule |