130 lines
5.4 KiB
Verilog
130 lines
5.4 KiB
Verilog
module effect_mixer #( parameter
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data_width = 16 // data width
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)(
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input clk,
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input [1:0] sw,
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input reset,
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input i_fifo_full,
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output signed [data_width-1: 0] o_data,
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output o_read_done, // read from effect module done
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output o_read_ready, // ready to read from effect module
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output o_data_valid, // data valit to write in FIFO memory
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input i_dv_from_eff,
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input signed [data_width-1: 0] i_data_from_eff_sw0, // Data output to effects module
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input signed [data_width-1: 0] i_data_from_eff_sw1
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);
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//-------------Internal Constants---------------------------
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localparam [2:0] IDLE = 'd0,
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ADD = 'd1,
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NORM = 'd2,
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OUTPUT = 'd3;
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reg [2:0] r_state=IDLE, r_next=IDLE;
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reg signed [data_width-1: 0] r_data_sw0 = 'b0;
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reg signed [data_width-1: 0] r_data_sw1 = 'b0;
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reg signed [data_width: 0] r_data_add = 'b0;
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reg signed [data_width-1: 0] r_data_norm = 'b0;
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reg r_read_done = 0;
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reg r_read_ready = 0;
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reg r_data_valid = 0;
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assign o_read_done = r_read_done;
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assign o_data_valid = r_data_valid;
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assign o_data = r_data_norm;
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assign o_read_ready = r_read_ready;
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//---------state register sequential always block-----------
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always @(posedge clk ) begin
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if (reset == 1) begin
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// clear state
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r_state <= IDLE;
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r_next <= IDLE;
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end
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else begin
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r_state <= r_next;
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end
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end
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//----next state & outputs, combinational always block------
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always @(posedge clk ) begin
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case(r_state)
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IDLE : begin
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if (i_dv_from_eff == 1) begin
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r_next <= ADD;
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r_data_sw0 <= i_data_from_eff_sw0;
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r_data_sw1 <= i_data_from_eff_sw1;
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r_data_norm <= 'b0;
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r_read_done <= 1;
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r_read_ready <= 0;
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r_data_valid <= 0;
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end
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else begin
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r_next <= IDLE;
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r_read_ready <= 1; // redy to read data
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r_data_valid <= 0;
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end
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end
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ADD : begin
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case ( sw )
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0 : begin // off all sound
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r_data_add <= 0;
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end
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1 : begin // no effect only
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r_data_add <= r_data_sw0;
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end
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2 : begin // clipping effect only
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r_data_add <= r_data_sw1;
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end
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3 : begin // no effect and clipping effect
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r_data_add <= r_data_sw0 + r_data_sw1;
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end
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endcase
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r_next <= NORM;
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r_read_done <= 0;
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end
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NORM : begin
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case ( sw )
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0 : begin // off all sound
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r_data_norm <= 0;
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end
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1 : begin // no effect only
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r_data_norm <= r_data_add[data_width-1: 0];
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end
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2 : begin // clipping effect only
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r_data_norm <= r_data_add[data_width-1: 0];
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end
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3 : begin // no effect and clipping effect
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r_data_norm <= r_data_add[data_width : 1] ; // Shift Right
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end
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endcase
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r_next <= OUTPUT;
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end
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OUTPUT : begin
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if ((i_fifo_full == 1) & (i_dv_from_eff == 1)) begin // wait for FIFO memory and data valid in effect module
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r_next <= OUTPUT;
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r_read_done <= 0;
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r_read_ready <= 0;
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r_data_valid <= 0;
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end
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else begin
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r_next <= IDLE;
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r_read_ready <= 0; // redy to read data
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r_data_valid <= 1; // data valid to write in FIFO
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end
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end
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default: r_next <= IDLE; // on error
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endcase
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end
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endmodule |