58 lines
1023 B
Verilog
58 lines
1023 B
Verilog
// This file is Test Bench for top_vga_mem module
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//
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//
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// 100MHz clock on Basys3 -> 10ns period
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// 50% duty cycle 5ns HIGH and 5ns LOW
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//`timescale [time unit] / [time precision]
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`timescale 10 ns / 1ns
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//top module
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`include "debounce_switch.v"
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module debounce_switch_tb();
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reg clk = 1'b0;
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reg btnC = 0;
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wire reset;
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// 50% duty cycle clock
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always #0.5 clk <= ~clk;
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debounce_switch UUT(
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.clk(clk),
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.i_switch(btnC),
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.o_switch(reset)
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);
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initial begin
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#20 btnC <= 1;
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#40 btnC <= 0;
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#40 btnC <= 1;
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#1_000_100 btnC <= 0;
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end
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initial begin
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#3_000_000;
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$display("*");
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$display(" ");
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$display("Use this command to open timing diagram:");
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$display("gtkwave -f wave.vcd");
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$display("----------------------------------------------");
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$finish();
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end
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initial
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begin
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$display(" ");
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$display("----------------------------------------------");
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$display(" Starting Testbench...");
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$dumpfile("wave.vcd");
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$dumpvars(0);
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end
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endmodule |