14 lines
230 B
Verilog
14 lines
230 B
Verilog
module d_flipflop_sync_rst(
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input D,
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output reg Q,
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input clk,
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input reset);
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always@(posedge clk, posedge reset)
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begin
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if(reset)
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Q <= 1'd0;
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else
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Q <= D;
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end
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endmodule |