107 lines
3.9 KiB
Verilog
107 lines
3.9 KiB
Verilog
module clipping_effect #( parameter
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data_width = 16 // data width
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)(
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input clk,
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input reset,
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input signed [data_width-1: 0] i_data,
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output signed [data_width-1: 0] o_data,
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input signed [data_width-1: 0] i_treshhold,
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input i_read_done,
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output o_read_enable,
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output o_data_valid,
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input i_data_ready
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);
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//-------------Internal Constants---------------------------
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localparam [1:0] IDLE = 'd0,
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CLIP = 'd1,
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OUTPUT = 'd2,
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CLEAR = 'd3;
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reg [1:0] r_state=IDLE, r_next=IDLE;
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reg signed [data_width-1: 0] r_data = 'b0;
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reg [data_width-1: 0] r_treshhold_p = 'b0;
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reg [data_width-1: 0] r_treshhold_n = 'b0;
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reg r_read_enable = 0;
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reg r_data_valid = 0;
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assign o_read_enable = r_read_enable;
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assign o_data_valid = r_data_valid;
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assign o_data = r_data;
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//---------state register sequential always block-----------
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always @(posedge clk ) begin
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if (~reset) begin
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r_state <= r_next;
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end
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end
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//----next state & outputs, combinational always block------
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always @(posedge clk ) begin
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if (reset) begin
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r_next <= IDLE;
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r_read_enable <= 0; // redy to read data
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r_data_valid <= 0;
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end
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else begin
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case(r_state)
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IDLE : begin
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if (i_data_ready == 1) begin
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r_next <= CLIP;
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r_data <= i_data;
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r_treshhold_p <= i_treshhold;
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r_treshhold_n <= (~i_treshhold) + 1; // two compliment
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r_read_enable <= 0;
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r_data_valid <= 0;
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end
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else begin
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r_next <= IDLE;
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r_read_enable <= 1; // redy to read data
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r_data_valid <= 0;
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end
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end
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CLIP : begin
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case (r_data[data_width-1])
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0 : begin // positive number
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if (r_data > r_treshhold_p) begin
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r_data <= r_treshhold_p; end
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end
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1 : begin // negative number
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if (r_data < r_treshhold_n) begin
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r_data <= r_treshhold_n; end
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end
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endcase
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r_next <= OUTPUT;
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r_data_valid <= 0;
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r_read_enable <= 0; // read disable
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end
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OUTPUT : begin
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if (i_read_done == 1) begin
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r_next <= CLEAR;
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r_data_valid <= 0;
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r_read_enable <= 0;
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end
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else begin
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r_next <= OUTPUT;
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r_data_valid <= 1;
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r_read_enable <= 0; // read disable
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end
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end
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CLEAR : begin
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r_next <= IDLE;
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r_data_valid <= 0;
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r_read_enable <= 1;
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end
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default: begin
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r_next <= IDLE; // on error
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end
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endcase
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end
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end
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endmodule |