Imants Pulkstenis
8da9e7da7c
i2s sender and i2s receiver. Also add JXADC_controler for logic analizer.
18 lines
442 B
Verilog
18 lines
442 B
Verilog
// This module outputs signals to JXADC PMOD
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// where logic analyzer are conected.
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module JXADC_controler (
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input ch0,
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input ch1,
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input ch2,
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input ch3,
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input ch4,
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input ch5,
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input ch6,
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input ch7,
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output [7: 0] JXADC // output for logic analizer
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);
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assign JXADC = {ch7,ch6,ch5,ch4,ch3,ch2,ch1,ch0};
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endmodule |