83 lines
3.1 KiB
Verilog
83 lines
3.1 KiB
Verilog
module io_module #( parameter
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sclk_ws_ratio = 64, // number of sclk periods per word select period
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mclk_sclk_ratio = 4, // number of mclk periods per sclk period
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d_width = 24 // data width
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)(
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//output reset, //asynchronous active low reset
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input mclk, //master clock
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output ad_sclk, //serial clock (or bit clock)
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output ad_ws, //word select (or left-right clock)
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output da_sclk, //serial clock (or bit clock)
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output da_ws, //word select (or left-right clock)
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output sd_tx, //serial data transmit
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input sd_rx, //serial data receive
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input signed [d_width-1: 0] l_data_tx, //left channel data to transmit
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input signed [d_width-1: 0] r_data_tx, //right channel data to transmit
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output signed [d_width-1: 0] l_data_rx, //left channel data received
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output signed [d_width-1: 0] r_data_rx, //right channel data received
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input reset,
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// inputs to logic analyzer
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input ch0,
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input ch1,
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input ch2,
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input ch3,
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input ch4,
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input ch5,
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input ch6,
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input ch7,
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output [7: 0] JXADC // output for logic analizer
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);
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i2s_sender #(
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.mclk_sclk_ratio(mclk_sclk_ratio), //number of mclk periods per sclk period
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.sclk_ws_ratio(sclk_ws_ratio), //number of sclk periods per word select period
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.d_width(d_width) //data width
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) i2s_sender (
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.reset_n(reset), //asynchronous active high reset
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.mclk(mclk), //master clock
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.sclk(da_sclk), //serial clock (or bit clock)
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.ws(da_ws), //word select (or left-right clock)
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.sd_tx(sd_tx), //serial data transmit
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.l_data_tx(l_data_tx), //left channel data to transmit
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.r_data_tx(r_data_tx) //right channel data to transmit
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);
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i2s_receicer #(
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.mclk_sclk_ratio(mclk_sclk_ratio), //number of mclk periods per sclk period
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.sclk_ws_ratio(sclk_ws_ratio), //number of sclk periods per word select period
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.d_width(d_width) //data width
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) i2s_receicer (
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.reset_n(reset), //asynchronous active high reset
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.mclk(mclk), //master clock
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.sclk(ad_sclk), //serial clock (or bit clock)
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.ws(ad_ws), //word select (or left-right clock)
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.sd_rx(sd_rx), //serial data receive
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.l_data_rx(l_data_rx), //left channel data received
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.r_data_rx(r_data_rx) //right channel data received
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);
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// connecting signals to JXADC PMOD to monitor them with signal analyzer
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JXADC_controler JXADC_controler(
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.ch0(ch0),
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.ch1(ch1),
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.ch2(ch2),
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.ch3(ch3), // serial data in
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.ch4(ch4),
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.ch5(ch5),
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.ch6(ch6),
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.ch7(ch7), // serial data out
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.JXADC(JXADC) // output for logic analizer
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);
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endmodule |